Articles

June 2nd, 2020

VHDL Users Also Deserve Efficient Design and Verification

Moving, tracing, and searching across multiple VHDL files helps when debugging errors or trying to understand a design

March 20th, 2020

An Interview with Open-Source “WaveDrom” Creator Aliaksei Chapyzhenka

Our customers specifically requested that we add waveform support via the WaveDrom open-source project

February 28th, 2020

An Important Step in Tackling the Debug Monster

Verissimo compares previous and current lint results to see whether the code has improved or degraded after changes

January 19th, 2020

Accelerate Your UVM Adoption and Usage With an IDE

The UVM Browser View is an intuitive entry point for exploring a UVM-based testbench, with elements grouped by categories

December 20th, 2019

Debugging Hardware Designs Using Software Capabilities

DVT Debugger provides all the interactive functionality that programmers enjoy, applied to design and verification code

November 21st, 2019

Accelerating the Adoption of Portable Stimulus

PSS support in DVT Eclipse IDE makes learning the DSL much easier and saves time in common operations, even for experts

October 16th, 2019

Achieving the Interactive Development of Low-Power Designs

DVT Eclipse IDE can be used to develop RTL and power intent files in parallel, keeping them in lockstep as both evolve

September 25th, 2019

Delivering on the Advanced Refactoring of Design and Verification Code

Refactoring makes code more readable and more maintainable, while making it more efficient for simulation and synthesis

September 16th, 2019

Automatic Documentation Generation for RTL Design and Verification

Specador produces professional-looking documentation, with different fonts and styles, hyperlinks, and generated diagrams

August 19th, 2019

Take Advantage of the Automated Refactoring of Design and Verification Code

Automatic refactoring provides an effective way to convert all code to a common format and produces more compact code