DVT SystemVerilog IDE User Guide
Rev. 21.1.8, 1 March 2021
You can easily explicitly declare an implicit net declaration.
Place the editor cursor on its name, press Ctrl+1, select Explicitly declare ... from the list of quick assist proposals and press Enter.
Note: The type of the new net declaration is automatically detected from context.
Tip: You may change the signal type. Press Enter when done.