DVT SystemVerilog IDE User Guide
Rev. 21.1.44, 19 October 2021

26.9 Explicitly Declare

You can easily explicitly declare an implicit net declaration.

Place the editor cursor on its name, press Ctrl+1, select Explicitly declare ... from the list of quick assist proposals and press Enter.

Note: The type of the new net declaration is automatically detected from context.

Tip: You may change the signal type. Press Enter when done.