DVT SystemVerilog IDE User Guide
Rev. 21.1.19, 10 May 2021
DVT can render bitfield diagrams from UVM register configurations in tooltips and in the Inspect View.
Trigger the tooltip from the Editor, by hovering a register class (a class that extends from uvm_reg) or a field of register class type:
Tip: To save the diagram as an SVG file, right-click on it in the Inspect View.
Note: Depending on the length of the reg field names, diagrams are drawn in a horizontal or vertical layout. By default the layout selection is done automatically.
Tip: To force a specific layout go to menu Window > Preferences then Diagrams > Bitfield Diagrams.