DVT IDE for VS Code SystemVerilog User Guide
Rev. 22.1.23, 16 August 2022
- Installation
- Predefined Projects
- Build Configurations
- Non-top files
- default.build
- Auto-config
- Simulator Log-config
- Emulating compiler invocations
- Multiple .build Files
- Compatibility Modes
- Paths
- Strings
- Comments
- Environment Variables
- Including Other Argument Files
- All Build Directives
- SystemVerilog OVM or UVM Library Compilation
- Xilinx Libraries Compilation
- Intel(Altera) Quartus Libraries Compilation
- Questa Libraries Compilation
- Use of External Programs
- Compile Checks
- Quick Fix Proposals
- Content Assist (Autocomplete)
- Hyperlinks
- Show Usages
- Show Readers or Writers
- Show Call Hierarchy
- Show Type Hierarchy
- Show Constraints
- Show Instances
- Peek Exploration
- Refactoring
- Override Functions
- Generate Setters and Getters
- Code Factory
- Code Formatting
- Breadcrumb Navigation Bar
- > Diagrams
- Syntax Coloring
- Tooltips
- Workspace Symbols
- Views
- Quick Search in Views
- Content Filters
- Macros Support
- UVM Support
- Scripts
- Custom Scripts
- SCM Checkout Hook
- Application Notes
- What is New?
- How to Report an Issue?
- Legal Notices
- Third Party Licenses
- Q & A
To display a UVM register bitfield diagram, you can:
hover over a register class (a class that extends from uvm_reg) or a field of register class type to see it in the tooltip
place the cursor on such an element and use the "DVT: Show Diagram" command
Note: Diagrams are rendered using the WaveDrom BitField library.