DVT VHDL IDE User Guide
Rev. 22.1.18, 15 June 2022

33.6.5 Performance

The following build config directives can restrict the elaboration and therefore improve performance when needed.

+dvt_elaboration_controlDisable steps in the elaboration from being performed.


Use NO_GENERATE_BLOCK_EVAL to disable any generate block condition evaluation. All branches of conditional generate blocks will be elaborated. Loop generate blocks will be elaborated only once.


Use NO_PARAM_EVAL to disable parameter evaluation. Parameters and constants will not have their values computed, not even their default values.


Use NO_WORK_PACKING to disable working memory packing.
E.g. +dvt_elaboration_control+NO_GENERATE_BLOCK_EVAL+NO_PARAM_EVAL
+dvt_elaboration_loop_block_cutoffConfigure the cut-off number for elaborated loop blocks.


In a design with many loop generate constructs, limiting the number to 1 per loop can drastically reduce the elaboration time.
E.g. +dvt_elaboration_loop_block_cutoff+1 (default: 200)
+dvt_elaboration_max_nof_resolve_binds_passesConfigure the maximum number of passes allowed when resolving bind directives.E.g. +dvt_elaboration_max_nof_resolve_binds_passes+1 (default:5)
+dvt_elaboration_disable_method_evalDisable function call evaluation in elaboration.E.g. +dvt_elaboration_disable_method_eval+true
+dvt_elaboration_skip_defparamsSkip defparam assignments during elaboration. E.g. +dvt_elaboration_skip_defparams+true
+dvt_elaboration_skip_modulesSkip elaboration of an instance based on design name.


Instance port connections and parameter overrides are checked but sub-instances are not elaborated.


Skipped designs are considered unelaborated. In the Design Hierarchy View, they are marked as SKIPPED.


Elaboration tops cannot be skipped.


Wildcards such as '*' (any string) and '?' (any character) can be used in the pattern.
E.g. +dvt_elaboration_skip_modules+*amod*
+dvt_elaboration_skip_pathsSkip elaboration of an instance based on design file absolute path.


Instance port connections and parameter overrides are checked but sub-instances are not elaborated.


Skipped designs are considered unelaborated. In the Design Hierarchy View, they are marked as SKIPPED.


Elaboration tops cannot be skipped.


Wildcards such as '*' (any string) and '?' (any character) can be used in the pattern.
E.g. +dvt_elaboration_skip_paths+/home/user/dvt_project/rtl/*
+dvt_elaboration_skip_instancesSkip elaboration of an instance based on hierarchical path.


Instance port connections and parameter overrides are checked but sub-instances are not elaborated.


Skipped designs are considered unelaborated. In the Design Hierarchy View, they are marked as SKIPPED.


Elaboration tops cannot be skipped.


Wildcards such as '*' (any string) and '?' (any character) can be used in the pattern.
E.g. +dvt_elaboration_skip_instances+top.dut.*

The following build config directives can restrict the functionality in the unelaborated code in order to improve performance.

+dvt_unelaborated_compile_checksControl the scope of the unelaborated design build checks and functionality.


If set to NONE, functionality and checking in the unelaborated modules and unelaborated local generate blocks is limited.


If set to GENERATE_BLOCKS, functionality and checking in all unelaborated modules is limited.


If set to DISCRETE, functionality and checking in the unelaborated modules found in library files is limited. This is the default value of the directive.


If set to FULL, functionality and checking is not limited in the unelaborated code.
E.g. +dvt_unelaborated_compile_checks+GENERATE_BLOCKS
+dvt_unelaborated_disable_package_constantsDisable unelaborated package constants evaluation and checking.E.g. +dvt_unelaborated_disable_package_constants+true