DVT VHDL IDE User Guide
Rev. 22.1.18, 15 June 2022
The unelaborated design is the part of the compiled code not under any of the elaboration tops. It can divided into two categories:
Tool functionality in the unelaborated part of the design can be restricted through the +dvt_unelaborated_compile_checks build config directive. A faster build time is the main benefit. But, the tradeoff is the loss of all IDE specific functionality, like for example Show Usages, Rename Refactoring, or Design Diagrams, in the excluded code.