October, 2014

AMIQ EDA Introduces New Capabilities in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA announced the release of new capabilities for dead code analysis and improved reporting of Pass/Fail checks in its Verissimo SystemVerilog Testbench Linter - a static code analysis tool for the SystemVerilog language and Universal Verification Methodology (UVM). The newly introduced capabilities enable engineers to further improve code performance and testbench reliability and reduce maintenance costs.

June, 2014

John Cooley - My Cheesy Must See List for DAC 2014

Their new Specador automatically generates HTML documentation.

June, 2014

Exhibitor at DAC 2014

AMIQ DVT Eclipse IDE and Specador on John Cooley's Cheesy Must See List for DAC 2014

June, 2014

AMIQ EDA Launches Specador Documentation Generator for e Language, SystemVerilog, Verilog, and VHDL Projects

Specador uses dedicated language parsers for e, SystemVerilog, Verilog, and VHDL to help design and verification engineers generate and maintain well-organized documentation with minimum effort.

March, 2014

DVCon 2014 Panel: Did We Create the Verification Gap?

The gap is more a matter of attitude. "Until recently, verification has been a second-class citizen in comparison to design." notes Cristian Amitroaie, CEO of AMIQ.