March, 2014

AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE

The key enhancements and new capabilities that DVT version 3.5 brings to its users include:

  • Enhanced compilation for SystemVerilog and VHDL
  • Improved UVM Support
  • Redesigned tool configuration and preference sharing capabilities
  • Streamlined GUI experience
June, 2013

John Cooley - My Cheesy Must See List for DAC 2013

Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
Amiq DVT Eclipse IDE provides IDE for design and verification languages like "e", System Verilog, VHDL. Visual C like stuff. Capacity. "Took one customer's 15 M lines of code, no problem."

March, 2013

What is that cool coding environment?

DVT is used by Cadence for training classes on Udacity. Don't forget we provide free licenses for academic use!

February, 2013
February, 2013

DVCon 2013 Cadence Verification Alliance Interview: "Support for mixed design and verification languages"

Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie. Discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.

February, 2013

AMIQ CEO explains how DVT editor supports e, SystemVerilog, Verilog, VHDL

Now, regardless of what language(s) your design/testbench was written in, you can use one environment to navigate seamlessly through large projects, easily see the big picture, and understand the whole design.
This cross-language integration does not mean translation from a language to another, but easy navigation through the source code, no matter in what language is written, using DVT's advanced navigation capabilities and unified perspective GUI. Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.

October, 2012

AMIQ EDA Announces Cross-Language Capabilities for Mixed-Language Projects

"Previous versions of the DVT IDE allowed users to work on projects that contained source code written in multiple languages, such as e, SystemVerilog, Verilog, and VHDL. However, some of the IDE’s specific editing and navigation features were restricted to the scope of a single language. Our goal has been to improve the cross-language integration and will continue to focus on this topic, in order to support the design and verification teams that have new or legacy code written in multiple languages, to increase their productivity."