DVCon 2013 Cadence Verification Alliance Interview: "Support for mixed design and verification languages"
Joseph Hupcey III speaks with Amiq CEO Cristian Amitroaie. Discuss trends in supporting the unavoidable mix of design & verification languages in simple work flows, and innovations supporting specific languages like SystemVerilog, e, and VHDL.
Now, regardless of what language(s) your design/testbench was written in, you can use one environment to navigate seamlessly through large projects, easily see the big picture, and understand the whole design.
This cross-language integration does not mean translation from a language to another, but easy navigation through the source code, no matter in what language is written, using DVT's advanced navigation capabilities and unified perspective GUI. Amiq Verissimo SV TB Linter performs code linting for generic System Verilog code and UVM.
"Readers of this blog and of Team Specman will recall that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting functional verification methodologies and testbench creation for years. The success of verification engineers using AMIQ's "DVT" IDE product has been increasingly noticed by their RTL designer colleagues such that AMIQ is now adding new capabilities to DVT to support RTL design work flows."
"At DVCon 2012, long time Cadence Connections Partner AMIQ launch new product -- the "Verissimo" SystemVerilog testbench linter is optimized for functional verification with UVM, and supports users adding their own custom rules. In this video AMIQ's CEO Cristian Amitroaie reviews the highlights of this exciting new offering."