Ensure an Effective Audit and Best Coding Practices with AMIQ's Verissimo SystemVerilog Testbench Linter
February 28, 2012, San Jose, California — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification, today announced the release of the Verissimo SystemVerilog Testbench Linter, a coding guideline and verification methodology compliance checker that enables engineers to perform an effective audit of their testbenches and helps them meet the requirements of today's complex functional verification.
With the Verissimo linter, verification engineers can check whether their code is free of language pitfalls and semantic or style issues as well as compliant with the appropriate methodologies, such as the Universal Verification Methodology (UVM), for instance. Verissimo can also be customized to check specific corporate coding guidelines to ensure consistency and best practices in code development at the company level.
The tool provides a comprehensive library of generic SystemVerilog and UVM checks. The UVM compliance-checking rules are written in accordance with the verification methodology guidelines from the UVM World. Users can create custom rule sets by selecting from the hundreds of built-in checks those that correspond to their requirements. They can also create new rules by using a dedicated Java application programming interface (API) delivered with the linter.
Verissimo runs both in batch and GUI modes and integrates with AMIQ's Design and Verification Tools (DVT) integrated development environment (IDE). Users can perform linting and then visualize the results in the DVT's GUI, which offers an easy way to read and understand the error and warning messages. In addition, the DVT's code navigation features, such as hyperlinks, allow the users to jump instantly to the problematic source line to fix the issue flagged by the linter.
In summary, AMIQ's Verissimo testbench linter can be customized to meet the demands of small teams up to larger verification groups and global companies. It helps improve testbench code reliability, functionality, and maintainability. The seamless integration between the Verissimo linter as a code analysis tool and the DVT IDE as a code development tool further improves the verification productivity and quality. It also contributes to decreasing the significant costs associated with code maintenance.
AMIQ is exhibiting at DVCon 2012, in San Jose, CA, February 28-29, booth #704 and showcasing the DVT IDE and Verissimo SystemVerilog Testbench Linter.
About AMIQ EDA
AMIQ EDA focuses on adding value to the design and verification domains through its proprietary code development and analysis tools. Since 2006, its core solution - Design and Verification Tools (DVT) - the first IDE for the e language, SystemVerilog, and VHDL, has helped engineers increase the speed and quality of code development and simplify debugging, enabling them to complete their projects faster. Its newer product - Verissimo SystemVerilog Testbench Linter - allows verification groups to improve testbench code reliability and functionality as well as implement best coding practices and their own specific guidelines. For more information about AMIQ EDA and its solutions, visit http://www.amiq.com.