Press Releases

February 26th, 2018

San Jose, California

AMIQ EDA Releases Version 18.1 of the Design and Verification Tools Eclipse IDE

AMIQ EDA announced version 18.1 of its flagship solution the DVT Eclipse IDE. The new version provides System-Level Notation (SLN) support, IEEE 1801/UPF/CPF power-intent specification formats support, breadcrumb navigation capabilities, automated FPGA projects bring-up, and more.

February 26th, 2018

San Jose, California

AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports IEEE Standard 1801 and CPF Power-Intent Specification Formats

AMIQ EDA announced its Design and Verification Tools (DVT) Eclipse IDE supports the two most popular formats for describing power intent in system-on-chip (SoC) designs with multiple power domains. AMIQ support the latest releases of both formats: IEEE Std. 1801-2015 - based on the Unified Power Format (UPF) - and Common Power Format (CPF) 2.0 from the Silicon Integration Initiative (Si2).

February 26th, 2018

San Jose, California

AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation

AMIQ EDA announced its Design and Verification Tools (DVT) Eclipse IDE supports the System-Level Notation (SLN) portable stimulus syntax developed by Cadence® Design Systems, Inc. for its Perspec™ System Verifier system-on-chip (SoC) verification solution.

January 30th, 2018

Redwood City, Califorina

AMIQ EDA Joins the ESD Alliance

The Electronic System Design Alliance (ESD Alliance), today confirmed AMIQ EDA of Bucharest, Romania, became a member of the growing international association of companies providing goods and services throughout the semiconductor design ecosystem.

February 27th, 2017

San Jose, California

AMIQ EDA Releases Version 17.1 of the Design and Verification Tools Eclipse IDE

AMIQ EDA announced version 17.1 of its flagship solution the DVT Eclipse IDE. The new version provides enhanced compilation capabilities, new state machine diagrams, new source code navigation features, and more.

February 27th, 2017

San Jose, California

AMIQ EDA Introduces UVM IEEE Compliance and Migration Capabilities

AMIQ EDA announced the release of new rules for UVM IEEE Compliance checking in Verissimo and new UVM IEEE specific refactoring operations in the DVT Eclipse IDE.

February 29th, 2016

San Jose, California

AMIQ EDA Unveils New Verilog and VHDL Design-Oriented Diagrams

AMIQ EDA unveils new Verilog and VHDL design-oriented diagrams that enable both design and verification engineers to easily visualize, explore, and understand RTL code.

June 8th, 2015

San Francisco, California

AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA announces new rules for duplicate code detection in its Verissimo SystemVerilog Testbench Linter to help design and verification engineers improve code quality and reduce maintenance costs.

March 3rd, 2015

San Jose, California

AMIQ EDA Releases the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL

AMIQ EDA announced the release of the DVT Debugger Add-On Module for the e language, SystemVerilog, Verilog, and VHDL, an extension to the DVT IDE that allows design and verification engineers perform debugging from the same place where they develop their code, in order to simplify and speed up debugging.

October 14th, 2014

Munich, Germany

AMIQ EDA Introduces New Capabilities in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA announced the release of new capabilities for dead code analysis and improved reporting of Pass/Fail checks in its Verissimo SystemVerilog Testbench Linter - a static code analysis tool for the SystemVerilog language and Universal Verification Methodology (UVM). The newly introduced capabilities enable engineers to further improve code performance and testbench reliability and reduce maintenance costs.