The DVT Eclipse IDE is a great tool. The productivity of a verification engineer using this tool is being increased greatly and the ROI is very noticeable.
Great tool! I have been using it for 6 years. It helps my team to improve the productivity and quality. The DVT Eclipse IDE is a must in our verification flow.
I have been using the DVT Eclipse IDE for the last 6 years, both for System Verilog and e/Specman Verification Environments and I must admit that DVT boosts substantially my productivity and efficiency. It reduces the development effort and helps meeting deadlines. I would not imagine myself using a plain editor or another EDA tool in the future. DVT fulfills all my development needs and is always updated to keep up with the new language constructs and methodologies.
The DVT Eclipse IDE has unique advantages providing easy navigation and tracing of signals in order to simplify the design integration tasks. The AMIQ support team goes the extra mile to make sure that the benefits from the tool are high.
The DVT Eclipse IDE is a great tool, to the point of being addictive. I got so used to it that I'm almost not able to understand someone else's code without it. Another thing which puzzles me is the astonishing rapidity of the AMIQ RnD in fixing reported issues. Keep up the good work!
I've been using the DVT Eclipse IDE for a few years now, in three different companies. DVT saves substantial time in my daily workload, so I am a big fan of the tool. I used it for both UVM verification and RTL design. The bigger the project, the bigger the savings.
DVT is an editor, parser, compiler, and checker in one tool. The navigation features include the ability to follow class inheritance and a type-based search and replace. The parser is good - it even found errors in the UVM standard library!
The DVT is often incorrectly compared to the regex-based editors, but it can do more than these tools are capable of. While the DVT cannot replace "the big three" (Cadence, Synopsys, Mentor), it complements them very well. AMIQ support is prompt and competent.
I am a big fan of the DVT Eclipse IDE. After several years of use, I find so many of its features useful in daily verification work. I also find that the engineers at AMIQ are great to interact with, and always improving an already powerful tool.
I have been using the DVT Eclipse IDE for a year. It is a tremendous productivity tool. It identifies syntax errors, eliminating multiple compilations to get past editing errors. The auto-completion of class method and module method names and fields is a major help. I do not have to go back to the defining code to get the correct spellings; I simply pick from a list. The editor will show you the the values of `defined macros. Similarly, the tool offers auto-completion of macro names. The code reformatting/pretty-printing feature works wonderfully. This just scratches the surface of the available features. I love it!
The DVT Eclipse IDE is a MUST HAVE for me. It is one of my main tools for productive VHDL coding which I like using every day because of:
- Powerful features: This plugin saves me precious development time through semantic-based auto completion and navigation, visualization of code, fast template insertion, partial recompilation and many more helpful features.
- Great stability: I could always rely on DVT. I cannot even remember a crash.
- Continuous development: Issues are solved fast and features are added regularly.
- Helpful, pleasant and responsive support: Whenever I had an issue, a question or a feature proposal, DVT development team was there to find a solution quickly.
Thank you AMIQ for having so much more fun writing VHDL code.
I strongly view the DVT Eclipse IDE as an essential element in the design and verification of complex designs; it is a well-integrated tool that not only allows correct-by-construction code per standard guidelines but provides users a very deep understanding of the design to facilitate debugging and communication.
What I loved about AMIQ EDA's DVT Eclipse IDE is that:
- it is a well thought-out, mature set of integrated tools for creating SystemVerilog and VHDL designs and verification environments (particularly UVM) such that the project is correct by construction;
- is supported by an in-depth structural and UML view of the architecture (including UVM and classes);
- is supported by a smart editor that understand the structure of the language and the structure of the design, thus providing features such as smart templates, auto-complete with list of potential objects; the editor can beautify code and declutter the view of code by hiding bodies of structures that are irrelevant to debugging (e.g., modules, functions, always, tasks, etc); ease of global rename changes (e,g., signal / function / module) using refactoring;
- automatically compiles code on the fly to detect coding errors;
- automatically generates html documentation about all information needed for the design (e.g., modules, interfaces, assertions, classes, macros, packages, covergoups);
- provides a smart SV linting including compliance to UVM best-use rules, and statistics about usage of sequences, assertions, coverage, and messaging).