Software Tools for Efficient Code Development and Analysis in Hardware Design and Verification

Verissimo SystemVerilog Testbench Linter

SystemVerilog provides powerful constructs and a high level of programming flexibility. Its capabilities meet today's complex design and verification requirements, but at the same time introduce new challenges in code development. For example, the ability to implement the same functionality in multiple ways may impact the simulation performance or lead to unexpected behavior.

A SystemVerilog compiler checks whether the source code follows the Language Reference Manual (LRM) rules and as such, it flags only language-specific syntactic and semantic errors. However, the absence of compilation errors does not give any indication of code reliability and maintainability. Nor does it implies that best coding practices have been implemented and compliancy with the recommended methodologies has been met.

Verissimo SystemVerilog Testbench Linter is a coding guideline and verification methodology compliance checker that enables engineers to perform an thorough audit of their testbenches. With this tool, users can check for language pitfalls, semantic and style issues, and compliance with the appropriate methodologies. Verissimo can be customized to check specific group or corporate coding guidelines to ensure consistency and best practices in code developing.

Verissimo SystemVerilog Testbench Linter Snapshots
  • Comprehensive library of generic SystemVerilog and Universal Verification Methodology (UVM) built-in checks
  • Custom rule sets configuration by re-categorizing, disabling, filtering, and re-grouping built-in checks
  • API for creating new custom checks
  • Rule severity adjustment
  • Waivers for exceptions and irrelevant failures
  • Rule annotation
  • Message filtering by source, category and severity
  • HTML analysis reporting including a dashboard that summarizes linting results, provides advanced searching and filtering capabilities, bookmarking and monitoring features
  • Batch or GUI mode
  • Integration with the DVT Eclipse IDE (GUI mode)
  1. Detect and fix early in the verification process:
    • Suspicious language usage such as non-standard syntax, problematic delta cycle usage, and prohibited system calls.
    • Semantic issues that are not caught by the SystemVerilog compiler, for example, an overridden non-virtual method, which will likely result in unexpected behavior.
    • Improper styling like confusing declaration order and naming conventions
    • Verification methodology violations such as inappropriate object creation, missing calls, and constructs that should be avoided
    • Unused code elements such as variables that are never read or written, or functions that are never called.
    • Performance issues like passing arrays by reference to avoid useless copies.
  2. Create, customize, and implement group or corporate-specific rules
  3. Ensure consistency in code developing at the team or company level
  4. Enforce best coding practices
  5. Reduce code maintenance costs

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