Press Releases

June 3rd, 2019

San Jose, California

AMIQ EDA Announces its Verissimo SystemVerilog Testbench Linter Supports Auto-Correction

AMIQ EDA today announced that the latest release of its Verissimo SystemVerilog Testbench Linter includes the ability to automatically correct violations found for certain classes of coding rules.

June 3rd, 2019

San Jose, California

AMIQ EDA Announces its DVT Eclipse IDE Supports Scenario Visualization for Portable Stimulus Models

AMIQ EDA today announced that its Design and Verification Tools (DVT) Eclipse IDE provides scenario visualization diagrams for models developed with the Portable Test and Stimulus Standard (PSS) 1.0a as released by Accellera Systems Initiative.

February 25th, 2019

San Jose, California

AMIQ EDA Releases Version 19.1 of the Design and Verification Tools Eclipse IDE

AMIQ EDA announced version 19.1 of its flagship solution the DVT Eclipse IDE. The new version provides easier navigation through automatically generated schematic diagrams, automatic generation of power supply network diagrams from power intent descriptions, verification breadcrumb bar for faster traversal of testbench code, scope breadcrumb bar for faster traversal of HDL code hierarchies, project database query and visualization capabilities for C/C++/SystemC code, and more.

July 11th, 2018

San Jose, California

AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports First Release of Accellera Portable Test and Stimulus Standard (PSS)

AMIQ EDA today announced its Design and Verification Tools (DVT) Eclipse IDE supports Portable Test and Stimulus Standard (PSS) 1.0 as released by Accellera Systems Initiative.

February 26th, 2018

San Jose, California

AMIQ EDA Releases Version 18.1 of the Design and Verification Tools Eclipse IDE

AMIQ EDA announced version 18.1 of its flagship solution the DVT Eclipse IDE. The new version provides System-Level Notation (SLN) support, IEEE 1801/UPF/CPF power-intent specification formats support, breadcrumb navigation capabilities, automated FPGA projects bring-up, and more.

February 26th, 2018

San Jose, California

AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports IEEE Standard 1801 and CPF Power-Intent Specification Formats

AMIQ EDA announced its Design and Verification Tools (DVT) Eclipse IDE supports the two most popular formats for describing power intent in system-on-chip (SoC) designs with multiple power domains. AMIQ support the latest releases of both formats: IEEE Std. 1801-2015 - based on the Unified Power Format (UPF) - and Common Power Format (CPF) 2.0 from the Silicon Integration Initiative (Si2).

February 26th, 2018

San Jose, California

AMIQ EDA Announces its Design and Verification Tools Eclipse IDE Supports Cadence Perspec System Verifier using System Level Notation

AMIQ EDA announced its Design and Verification Tools (DVT) Eclipse IDE supports the System-Level Notation (SLN) portable stimulus syntax developed by Cadence® Design Systems, Inc. for its Perspec™ System Verifier system-on-chip (SoC) verification solution.

January 30th, 2018

Redwood City, Califorina

AMIQ EDA Joins the ESD Alliance

The Electronic System Design Alliance (ESD Alliance), today confirmed AMIQ EDA of Bucharest, Romania, became a member of the growing international association of companies providing goods and services throughout the semiconductor design ecosystem.

February 27th, 2017

San Jose, California

AMIQ EDA Releases Version 17.1 of the Design and Verification Tools Eclipse IDE

AMIQ EDA announced version 17.1 of its flagship solution the DVT Eclipse IDE. The new version provides enhanced compilation capabilities, new state machine diagrams, new source code navigation features, and more.

February 27th, 2017

San Jose, California

AMIQ EDA Introduces UVM IEEE Compliance and Migration Capabilities

AMIQ EDA announced the release of new rules for UVM IEEE Compliance checking in Verissimo and new UVM IEEE specific refactoring operations in the DVT Eclipse IDE.