Press Releases
San Francisco, California
AMIQ EDA Adds Runtime Elaboration of UVM Testbench Code to DVT Eclipse IDE
By performing the runtime elaboration of SystemVerilog verification environments compliant with the Universal Verification Methodology (UVM), DVT Eclipse IDE now enables users to view their testbench structures accurately reflecting the configuration at the start of simulation.
Bucharest, Romania
AMIQ Celebrates 20 Successful Years in Semiconductor Design and Verification
We started AMIQ to help our customers be successful, to work with the best talent, and to give something back to our community.
San Jose, California
AMIQ EDA to Demonstrate Enhanced IDE Performance at DVCon U.S.
The first 2023 release of the AMIQ EDA products contains significant performance improvements to enhance the user experience.
San Jose, California
AMIQ EDA to Demonstrate New IDE Capabilities at DVCon Europe and SemIsrael
The two exhibit booths will focus on two new capabilities that have proven very popular with users.
San Jose, California
AMIQ EDA Adds Support for Arm AArch64 Architecture
“We are seeing broader Arm adoption across the EDA ecosystem to improve design and verification tools for engineers,” said Tran Nguyen, senior director of design services, Arm. “It is a milestone achievement for the Arm ecosystem to have full support for AMIQ EDA software tools that enable increased speed of development for future computing platforms.”
San Jose, California
AMIQ EDA Adds Support for Visual Studio Code to DVT Integrated Development Environment Family
Chip developers now have their choice of platform underlying the industry’s most powerful interactive design and verification solution.
San Jose, California
AMIQ EDA Joins OpenHW Group and Contributes Linting Capabilities for CORE-V Open-Source RISC-V Cores and Testbenches
“Simulators and other electronic design automation (EDA) tools detect some types of coding errors, but the OpenHW team was looking for a dedicated linting tool with more capabilities,” said Cristian Amitroaie, CEO of AMIQ EDA. “Our solution detects many types of issues, checking more than 700 rules for SystemVerilog and the Universal Verification Methodology (UVM), and offers suggestions for resolving them. Developers and users of OpenHW Group testbenches can be certain that their code is correct and follows industry best practices.”
Bucharest, Romania
AMIQ EDA Achieves ISO 9001 Quality Standard Certification
We are proud of our product development flow and other processes, and we continually strive for the highest quality.
San Jose, California
AMIQ EDA Updates UVM Rule Checks for Latest Release of the Universal Verification Methodology Standard
“The UVM, like many standards, evolves significantly with each new version,” said Cristian Amitroaie, CEO of AMIQ EDA. “We are pleased to ensure that our users remain compliant by avoiding outdated aspects of the API while helping them to use new functionality quickly and easily.”
San Jose, California
AMIQ Consulting Wins Third Place Stuart Sutherland Best Paper Award at DVCon U.S.
Open-Source Framework for Co-Emulation Using PYNQ” has received the Stuart Sutherland Best Paper third place award at the Design and Verification Conference (DVCon) U.S. Ioana Catalina Cristea and Dragos Dospinescu of AMIQ Consulting co-authored the paper and presented the results at the virtual conference.