3.3.3 ius.irun Compatibility Mode

The +dvt_init+ius.irun directive resets the builder to the ius.irun default state.

File Extension to Language Syntax Mapping

Syntax	Extensions
Verilog 1995	.v95, .v95p
Verilog AMS 2.3	.vams
Verilog 2001	.v, .vp, .vs
System Verilog 1800-2012	.sv, .svp, .svi, .svh, .vlib, .vcfg
System Verilog AMS	.svams
VHDL 1987	.vhd, .vhdl, .vhdp, .vhdlp, .vhcfg
VHDL AMS 1999	.vha, .vhams, .vhms
VHDL 2008	.pslvhdl
e Language 1647-2011	.e
C/c++	.c, .h, .cc, .cpp, .cxx, .pslsc
Shared objects (C/C++ libraries)	.o, .a, .so, .sl
Skipped Files	.pslvlog, .s, .scs, .sp

Language Syntax for Unmapped Extensions: Skip

Language Syntax for Included Files: Included files are parsed using the syntax that was used for parsing the including file.

Mode Specific Directives

Note: in IUS compatibility mode all directives are case-insensitive except for -f / -F

Note: in IUS compatibility mode, top and test files specified using relative paths are solved, in order, as relative to the compilation root, then $SPECMAN_PATH entries

Directive	Description
-ams	All files that would be parsed with a Verilog / VHDL syntax flavor will be parsed with Verilog AMS 2.3 / VHDL AMS 1999 instead. Has precedence over other syntax specifications.
-amscompilefile "file:<file_path>[ ...]"	Equivalent with specifying <file_path> as a top file.
-asext <ext>[,<ext>]	Equivalent to -as_ext +<ext>[,<ext>]
-ccext <ext>	Equivalent to -c_ext +<ext>[,<ext>]
-cxxext <ext>	Equivalent to -cpp_ext +<ext>[,<ext>]
-default_ext <syntax>	Set the Language Syntax for Unmapped Extensions. See the list below for more details regarding the <syntax> argument.
-lps_1801 <upf_file>	Specify a Unified Power Format file to be analyzed.
-lps_cpf <cpf_file>	Specify a Common Power Format file to be analyzed.
-makelib <lib_name> ... -endlib -makelib /path/to/ <lib_name> ... -endlib -makelib /some/path: <lib_name> ... -endlib	Compiles files specified inside a - makelib ... - endlib section into the <lib_name> library. Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation. The - work directive is ignored within a makelib section.
-objext <ext>	Equivalent to -o_ext +<ext>[,<ext>]
-ovm -uvm	Load the OVM / UVM library from the IUS installation location. For ovm: `ncroot`/tools/methodology/OVM/CDNS-2.1.2 or `ncroot`/tools/ovm if the first does not exist. For uvm: `ncroot`/tools/methodology/UVM/CDNS-1.1d/sv or `ncroot`/tools/uvm/uvm_lib/uvm_sv if the first does not exist. NOTE: If the path to OVM/UVM cannot be located within the IUS installation, the tool tries to load the library from $OVM_HOME or $DVT_OVM_HOME (resp. $UVM_HOME or $DVT_UVM_HOME). If $DVT_OVM_HOME is not defined, falls back to $DVT_HOME/predefined_projects/libs/ovm-2.1.2. If $DVT_UVM_HOME is not defined, falls back to $DVT_HOME/predefined_projects/libs/uvm-1.2.
-ovmhome <path> -uvmhome <path>	If <path> is: the word "default": equivalent with -ovm / -uvm an existing absolute path or relative path: load the OVM / UVM library from the specified <path> an existing subpath of `ncroot`/tools/methodology/OVM/: load the OVM library from `ncroot`/tools/methodology/OVM/<path> an existing subpath of `ncroot`/tools/methodology/UVM/: load the UVM library from `ncroot`/tools/methodology/UVM/<path>/sv Has precedence over -ovm / -uvm.
-ml_uvm	Load the UVM_ML library from the IUS installation location. For uvm: `ncroot`/tools/methodology/UVM/CDNS-1.1d/ml. NOTE: If the path to UVM_ML cannot be located within the IUS installation, the tool tries to load the library from $UVM_HOME or $DVT_UVM_HOME.
-uvmexthome <path>	If <path> is an existing absolute path or relative path: load the UVM extension files from the specified <path>. Should be used in conjunction with '-uvmhome'.
-pkgsearch <lib>	Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
-snpath <path>	Equivalent to +dvt_setenv+SPECMAN_PATH=$SPECMAN_PATH:<path>
-sndefine <arg>	Equivalent to +define+<arg>
-sv	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a Verilog syntax flavor will be parsed with SystemVerilog 2012 instead. Has precedence over -v1995.
-svams_2019	All Verilog/SystemVerilog files will be parsed with SystemVerilog AMS. Has precedence over other syntax specifications.
-<syntax>_ext [+]<ext>[,<ext>]	Files with <ext> extension will be parsed using the specified <syntax>. If the optional + is specified, the mapping will be added to the default File Extension to Language Syntax Mapping. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default File Extension to Language Syntax Mapping will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - vlog_ext .svh,.svp. The dot (.) for specifying <ext> is mandatory. The following directives are supported: -a_ext, -amsvhdl_ext, -amsvlog_ext, -as_ext, -c_ext, -cpp_ext, -dynlib_ext, -e_ext, -o_ext, -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext. See the list below for more details regarding <syntax>.
-v1995 -v95	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with Verilog 2001 will be parsed instead with a reduced keywordset variant of Verilog 2001. The reduced keywordset does not contain the keywords automatic, localparam, generate, endgenerate, and genvar.
-v200x	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 2008 instead. Has precedence over -v93.
-v93	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 93 instead.
-vhdlext <ext>	Equivalent to -vhdl_ext +<ext>[,<ext>]
-vlogext <ext>	Equivalent to -vlog_ext +<ext>[,<ext>]

How to specify <syntax> for - default_ext <syntax> and - <syntax>_ext directives

Language Syntax	- default_ext <syntax>	- <syntax>_ext
Verilog 2001	-default_ext verilog	-vlog_ext
Verilog 1995	-default_ext verilog95	N/A
SystemVerilog 2012	-default_ext systemverilog, -default_ext vcnf	-sysv_ext
VHDL 1987	-default_ext vhdl, -default_ext vhcfg	-vhdl_ext
e Language	-default_ext e	-e_ext
VHDL AMS 1999	-default_ext vhdl-ams	-amsvhdl_ext
SKIP	-default_ext verilog-ams, -default_ext psl_vlog, -default_ext psl_vhdl, -default_ext psl_sc, -default_ext c, -default_ext cpp, -default_ext assembly, -default_ext o, -default_ext a, -default_ext so, -default_ext scs	-a_ext, -amsvhdl_ext, -amsvlog_ext, -as_ext, -c_ext, -cpp_ext, -dynlib_ext, -e_ext, -o_ext, -spice_ext, -sysv_ext, -vhcfg_ext, -vhdl_ext

Predefined API

INCA	Defined as preprocessing macro without value.

Examples

I want to parse .sv, .c and .v files as SystemVerilog:

+dvt_init+ius.irun // By default .c are skipped and .v are parsed with Verilog 2001 syntax
-sysv_ext +.v,.c // Now .c and .v are parsed with SystemVerilog 2012; however, the default extensions mapped to SystemVerilog 2012 still stand, including .sv

Note Every time you re-map an already mapped extension, DVT will warn you. For the example above, you get the following warnings:

.v was previously mapped to Verilog_2001
.c was previously mapped to Skip

I want the .vp files to be parsed with the Language Syntax for Unmapped Extensions:

+dvt_init+ius.irun // By default .vp, .v, .vs are parsed with Verilog 2001
-vlog_ext .v, .vs // We override the mapping for Verilog 2001 with only the other two extensions.
// Now .vp is not mapped to any Language Syntax.
// Because by default the unmapped extensions are skipped, .vp files will be skipped

I want to change the Language Syntax for Unmapped Extensions:

+dvt_init+ius.irun // By default the unmapped extensions are skipped
-default_ext verilog95 // Now unmapped extensions, for example .foo, will be parsed as Verilog 95

I want to parse all Verilog source files and all files with unmapped extensions as SystemVerilog, and all VHDL files as VHDL 2000:

+dvt_init+ius.irun
-default_ext systemverilog // All files with unmapped extensions are parsed as SystemVerilog
-sv // All Verilog source files are parsed with SystemVerilog
-v200x // All VHDL source files are parsed with VHDL 2008