DVT IDE for VS Code VHDL User Guide
Rev. 22.1.29, 28 September 2022

DVT IDE for VS Code VHDL User Guide

Table of Contents

1. Installation
1.1. System Requirements
1.2. Install DVT for VS Code from Marketplace
1.3. Install DVT for VS Code from VSIX
1.4. Install DVT for VS Code Using a Pre-Packed Distribution
1.5. Set the License
2. Predefined Projects
3. Build Configurations
3.1. Non-top files
3.2. default.build
3.3. Auto-config
3.4. Simulator Log-config
3.5. Emulating compiler invocations
3.6. Multiple .build Files
3.7. Compatibility Modes
3.7.1. Default DVT Compatibility Mode
3.7.2. gcc Compatibility Mode
3.7.3. ius.irun Compatibility Mode
3.7.4. ius.perspec Compatibility Mode
3.7.5. questa.vcom Compatibility Mode
3.7.6. questa.vlog Compatibility Mode
3.7.7. vcs.vhdlan Compatibility Mode
3.7.8. vcs.vlogan Compatibility Mode
3.7.9. xcelium.xrun Compatibility Mode
3.8. Paths
3.9. Strings
3.10. Comments
3.11. Environment Variables
3.12. Including Other Argument Files
3.13. All Build Directives
3.14. SystemVerilog OVM or UVM Library Compilation
3.15. Xilinx Libraries Compilation
3.16. Intel(Altera) Quartus Libraries Compilation
3.17. Questa Libraries Compilation
3.18. Use of External Programs
4. Compile Checks
4.1. Compile Waivers
4.2. Semantic Checks
4.3. Non Standard Checks
5. Quick Fix Proposals
6. Content Assist (Autocomplete)
6.1. Content assist for CamelCase and Underscore
6.2. Code Templates
6.3. Component Automatic Instantiation
6.4. Generate Case Statement Using Autocomplete
7. Hyperlinks
8. Show Usages
9. Show Readers or Writers
10. Show Instances
11. Peek Exploration
12. Refactoring
13. Code Factory
14. Code Formatting
14.1. Capitalization
14.2. Whitespace
14.3. Indentation
14.4. Vertical Alignment
14.5. Line Wrapping
14.6. Disable Format for Code Sections
15. Breadcrumb Navigation Bar
15.1. Design Breadcrumb
15.2. Verification Breadcrumb
15.3. Scope Breadcrumb
16. Diagrams
16.1. Design Diagrams
16.1.1. Schematic Diagrams
16.1.2. Flow Diagrams
16.1.3. Block Diagrams
16.1.4. Finite-State Machine Diagrams
16.1.5. Design Diagram Actions
16.1.6. Design Diagram Filters
16.2. WaveDrom Timing Diagrams
16.3. Common Diagram Actions
16.4. Common Diagram Toolbar
17. Syntax Coloring
18. Tooltips
18.1. Comments Formatting
18.1.1. Javadoc
18.1.2. Natural Docs
19. Workspace Symbols
20. Views
20.1. Problems View
20.2. Outline View
20.3. Compiled Files View
20.4. Compile Order View
20.5. Design Hierarchy View
20.6. Diagnostics View
21. Quick Search in Views
21.1. CamelCase
21.2. Simple Regex
21.3. Hierarchical Search
21.4. Search for Members
21.5. Search Port in Design Hierarchy
22. Content Filters
22.1. Content Filters XML Syntax
22.2. Filtering by Element Type
22.3. Content Filters Examples
22.4. Predefined Content Filters
23. Scripts
23.1. dvt_code.sh
23.1.1. dvt_code.sh Syntax
23.1.2. dvt_code.sh Examples
23.2. dvt_ls.sh
23.2.1. dvt_ls.sh Syntax
23.2.2. dvt_ls.sh Examples
24. Custom Scripts
25. SCM Checkout Hook
26. Application Notes
26.1. Flow Integration
26.2. Environment Variables
26.3. FPGA Support
26.3.1. Intel(Altera) Quartus
26.3.2. Xilinx ISE/Vivado
27. What is New?
28. How to Report an Issue?
29. Legal Notices
30. Third Party Licenses
31. Q & A
31.1. Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?