DVT IDE for VS Code VHDL User Guide
Rev. 23.1.21, 12 September 2023
The Code Factory allows you to easily generate instances, signals, and testbenches starting with modules or entities.
It is required that you first set an input. Place the cursor on a SystemVerilog module, interface, program, checker, or a VHDL entity definition and use the "DVT: Set Code Factory Input" command.
The current input persists until it is cleared ( "DVT: Clear Code Factory Input" command) or until a new one is set. Invoking a full build will also clear the current input.
Having set an input, you can use the "Trigger Suggest" command in order to do one of the following:
The code will be inserted at the cursor's current position.
Any information or errors during Code Factory operations are shown via notifications.
You can customize the output of the Code Factory using FreeMarker Templates. API is available on the FreeMarker model root.
In the script template you can access structured data describing the design which has been set as factory input. The design is represented by the model root.
The following API is accessible in the FreeMarker template:
<#assign entity = root>
<#--Determine the max length for ports -->
<#--print ports -->
Note: Cross language operations are not supported. You can't set a SystemVerilog module as input and use it in VHDL for creating output and vice-versa.