<!--
Each filter may specify a view-set tag.
If view-set is not specified, the filter applies to all views.
The view-set tag must specify a match attribute.
If match="TRUE" the set comprises of the enumerated views (see below).
If match="FALSE" the set comprises all views except the enumerated ones (see below).
-->
<view-set match="TRUE">
<!--
A view-set must contain at least one view tag. The view tag must
specify the name attribute. Possible values for the name attribute are: CALL_HIERARCHY,
COMPILE_ORDER, DESIGN_HIERARCHY, DIAGRAM, MACRO, OUTLINE, PROBLEMS,
TYPES, UVM_SEQUENCE_TREE, VERIFICATION_HIERARCHY
-->
<view name="TASKS" />
</view-set>
<!--
The path-set tag must specify a match attribute.
If match="TRUE" the set comprises of the enumerated paths (see below).
If match="FALSE" the set comprises any path except the enumerated ones (see below).
An element (problem, task, type, function, macro etc) matches the path-set if it is
defined/introduced in a file within the path-set.
The path-set tag may specify an apply-to-macro-call-stack attribute.
By default apply-to-macro-call-stack="FALSE".
If apply-to-macro-call-stack="TRUE" an element introduced by a macro call will
match the path set if the macro matches the path-set.
-->
<path-set match="TRUE" apply-to-macro-call-stack="TRUE">
<!--
A path-set must contain at least a path attribute.
The path tag must specify a pattern attribute.
The pattern may contain wildcards ? (any character) and * (any sequence of characters).
The pattern may contain environment variables. You may not use
variables defined in build configuration files using +dvt_env+ directive.
The path tag may specify an include-children attribute.
By default include-children="FALSE".
If include-children="TRUE" any file `included (SystemVerilog)
directly or indirectly by a file matching the pattern, is also part of the path-set.
-->
<path pattern="*/uvm_pkg.sv" include-children="TRUE" />
</path-set>
<!--
The element-type-set tag must specify a match attribute.
If match="TRUE", an element matches if it matches any element-type tag.
If match="FALSE", an element matches if it does not match any element-type tag.
-->
<element-type-set match="TRUE">
<!--
An element-type-set must contain at least one element-type tag.
The element-type tag must specify the name attribute.
Valid values for the element-type name are:
ACTION, ACTIVITY, ALIAS, ARCHITECTURE, ASSERT, BLOCK, CHECK, CHECKER, CHECKER_INSTANCE,
CLASS, CLOCKING_BLOCK, COMPONENT, CONFIGURATION, CONSTRAINT, COVER_CROSS, COVER_GROUP,
COVER_POINT, COVER_TRANSITION, ENTITY, EVENT, EXEC_BLOCK, EXPECT, FIELD, FUNCTION,
GENERATE_BLOCK, INSTANCE, INTERFACE, INTERFACE_INSTANCE, LIBRARY, LINKAGE, MACRO, METHOD,
METHOD_TYPE, MODPORT, MODULE, MODULE_INSTANCE, NAMESPACE, ONEVENT, PACKAGE, PACKAGE_BODY,
PACKAGE_INSTANCE, PARAMETER, PORT, PRIMITIVE, PROCESS, PROGRAM, PROGRAM_INSTANCE,
PROPERTY_SEQUENCE, SIGNAL, STRUCT, SUBPROGRAM_INSTANCE, TASK, TOKEN, TYPE, TYPE_PARAMETER,
TYPEDEF, UNION, VARIABLE, VUNIT
-->
<!--
The element-type tag may specify a language attribute which helps to fully identify
an element which is valid in multiple languages (for example STRUCT is a valid element
type both in SystemVerilog and e Language)
The valid values for the language attribute are: SV and VHDL.
-->
<element-type name="STRUCT" language="SV" />
</element-type-set>
<!--
The element-text-set tag must specify a match attribute.
If match="TRUE", an element matches the set if it matches any element-text tag.
If match="FALSE", an element matches the set if it does not match any element-text tag.
An element (problem, task, type, function, macro etc) matches the text-set if its displayed
label matches the text-set.
-->
<element-text-set match="TRUE">
<!--
An element-text-set must contain at least one element-text tag.
The element-text tag must specify a pattern attribute.
The pattern may contain wildcards ? (any character) and * (any sequence of characters).
-->
<element-text pattern="_internal_*"/>
</element-text-set>
</filter>
</content-filters>