DVT IDE for VS Code SystemVerilog User Guide
Rev. 22.1.29, 28 September 2022
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Installation
System Requirements
Install DVT for VS Code from Marketplace
Install DVT for VS Code from VSIX
Install DVT for VS Code Using a Pre-Packed Distribution
Set the License
Predefined Projects
Build Configurations
Non-top files
default.build
Auto-config
Simulator Log-config
Emulating compiler invocations
Multiple .build Files
Compatibility Modes
Default DVT Compatibility Mode
gcc Compatibility Mode
ius.irun Compatibility Mode
ius.perspec Compatibility Mode
questa.vcom Compatibility Mode
questa.vlog Compatibility Mode
vcs.vhdlan Compatibility Mode
vcs.vlogan Compatibility Mode
xcelium.xrun Compatibility Mode
Paths
Strings
Comments
Environment Variables
Including Other Argument Files
All Build Directives
SystemVerilog OVM or UVM Library Compilation
Xilinx Libraries Compilation
Intel(Altera) Quartus Libraries Compilation
Questa Libraries Compilation
Use of External Programs
Compile Checks
Compile Waivers
Semantic Checks
Synthesis Checks
Performance Checks
Dead Code Checks
Non Standard Checks
Quick Fix Proposals
Content Assist (Autocomplete)
Content Assist for CamelCase and Underscore
Code Templates
Module Automatic Instantiation
Override Functions Using Autocomplete
Implement Extern Functions Using Autocomplete
Generate Setters and Getters Using Autocomplete
Use Assignment Pattern for Struct Type Variable
Hyperlinks
Show Usages
Show Readers or Writers
Show Call Hierarchy
Show Type Hierarchy
Show Constraints
Show Instances
Peek Exploration
Refactoring
Override Functions
Override Annotation
Override Using Command Palette
Override Using Autocomplete
Generate Setters and Getters
Code Factory
Code Formatting
Whitespace
Indentation
Vertical Alignment
Line Wrapping
Disable Format for Code Sections
Breadcrumb Navigation Bar
Design Breadcrumb
Verification Breadcrumb
Scope Breadcrumb
Diagrams
UML Diagrams
UML Diagram Actions
UML Diagram Preferences
UML Diagrams Legend
Design Diagrams
Schematic Diagrams
Flow Diagrams
Block Diagrams
Finite-State Machine Diagrams
Design Diagram Actions
Design Diagram Filters
UVM Components Diagrams
Component Diagrams from Verification Hierarchy
Component Diagrams from Simulation
Component Diagram Actions
Component Diagram Preferences
Component Diagram Filters
WaveDrom Timing Diagrams
UVM Register Bitfield Diagrams
Common Diagram Actions
Common Diagram Toolbar
Syntax Coloring
Tooltips
Comments Formatting
Javadoc
Natural Docs
Workspace Symbols
Views
Problems View
Outline View
Compiled Files View
Compile Order View
Design Hierarchy View
Verification Hierarchy View
Diagnostics View
Quick Search in Views
CamelCase
Simple Regex
Hierarchical Search
Search for Members
Search Port in Design Hierarchy
Search Port in Verification Hierarchy
Content Filters
Content Filters XML Syntax
Filtering by Element Type
Content Filters Examples
Predefined Content Filters
Macros Support
Inactive Code Highlight
Macro Expansion
UVM Support
Show UVM Sequence Tree
Scripts
dvt_code.sh
dvt_code.sh Syntax
dvt_code.sh Examples
dvt_ls.sh
dvt_ls.sh Syntax
dvt_ls.sh Examples
Custom Scripts
SCM Checkout Hook
Application Notes
Flow Integration
Environment Variables
Encrypted VIP Support
FPGA Support
Intel(Altera) Quartus
Intel(Altera) Quartus Libraries Compilation
Xilinx ISE/Vivado
Xilinx Libraries Compilation
What is New?
How to Report an Issue?
Legal Notices
Third Party Licenses
Q & A
Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?
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DVT IDE for VS Code SystemVerilog User Guide
Table of Contents
1. Installation
1.1. System Requirements
1.2. Install DVT for VS Code from Marketplace
1.3. Install DVT for VS Code from VSIX
1.4. Install DVT for VS Code Using a Pre-Packed Distribution
1.5. Set the License
2. Predefined Projects
3. Build Configurations
3.1. Non-top files
3.2. default.build
3.3. Auto-config
3.4. Simulator Log-config
3.5. Emulating compiler invocations
3.6. Multiple .build Files
3.7. Compatibility Modes
3.7.1. Default DVT Compatibility Mode
3.7.2. gcc Compatibility Mode
3.7.3. ius.irun Compatibility Mode
3.7.4. ius.perspec Compatibility Mode
3.7.5. questa.vcom Compatibility Mode
3.7.6. questa.vlog Compatibility Mode
3.7.7. vcs.vhdlan Compatibility Mode
3.7.8. vcs.vlogan Compatibility Mode
3.7.9. xcelium.xrun Compatibility Mode
3.8. Paths
3.9. Strings
3.10. Comments
3.11. Environment Variables
3.12. Including Other Argument Files
3.13. All Build Directives
3.14. SystemVerilog OVM or UVM Library Compilation
3.15. Xilinx Libraries Compilation
3.16. Intel(Altera) Quartus Libraries Compilation
3.17. Questa Libraries Compilation
3.18. Use of External Programs
4. Compile Checks
4.1. Compile Waivers
4.2. Semantic Checks
4.3. Synthesis Checks
4.4. Performance Checks
4.5. Dead Code Checks
4.6. Non Standard Checks
5. Quick Fix Proposals
6. Content Assist (Autocomplete)
6.1. Content Assist for CamelCase and Underscore
6.2. Code Templates
6.3. Module Automatic Instantiation
6.4. Override Functions Using Autocomplete
6.5. Implement Extern Functions Using Autocomplete
6.6. Generate Setters and Getters Using Autocomplete
6.7. Use Assignment Pattern for Struct Type Variable
7. Hyperlinks
8. Show Usages
9. Show Readers or Writers
10. Show Call Hierarchy
11. Show Type Hierarchy
12. Show Constraints
13. Show Instances
14. Peek Exploration
15. Refactoring
16. Override Functions
16.1. Override Annotation
16.2. Override Using Command Palette
16.3. Override Using Autocomplete
17. Generate Setters and Getters
18. Code Factory
19. Code Formatting
19.1. Whitespace
19.2. Indentation
19.3. Vertical Alignment
19.4. Line Wrapping
19.5. Disable Format for Code Sections
20. Breadcrumb Navigation Bar
20.1. Design Breadcrumb
20.2. Verification Breadcrumb
20.3. Scope Breadcrumb
21. Diagrams
21.1. UML Diagrams
21.1.1. UML Diagram Actions
21.1.2. UML Diagram Preferences
21.1.3. UML Diagrams Legend
21.2. Design Diagrams
21.2.1. Schematic Diagrams
21.2.2. Flow Diagrams
21.2.3. Block Diagrams
21.2.4. Finite-State Machine Diagrams
21.2.5. Design Diagram Actions
21.2.6. Design Diagram Filters
21.3. UVM Components Diagrams
21.3.1. Component Diagrams from Verification Hierarchy
21.3.2. Component Diagrams from Simulation
21.3.3. Component Diagram Actions
21.3.4. Component Diagram Preferences
21.3.5. Component Diagram Filters
21.4. WaveDrom Timing Diagrams
21.5. UVM Register Bitfield Diagrams
21.6. Common Diagram Actions
21.7. Common Diagram Toolbar
22. Syntax Coloring
23. Tooltips
23.1. Comments Formatting
23.1.1. Javadoc
23.1.2. Natural Docs
24. Workspace Symbols
25. Views
25.1. Problems View
25.2. Outline View
25.3. Compiled Files View
25.4. Compile Order View
25.5. Design Hierarchy View
25.6. Verification Hierarchy View
25.7. Diagnostics View
26. Quick Search in Views
26.1. CamelCase
26.2. Simple Regex
26.3. Hierarchical Search
26.4. Search for Members
26.5. Search Port in Design Hierarchy
26.6. Search Port in Verification Hierarchy
27. Content Filters
27.1. Content Filters XML Syntax
27.2. Filtering by Element Type
27.3. Content Filters Examples
27.4. Predefined Content Filters
28. Macros Support
28.1. Inactive Code Highlight
28.2. Macro Expansion
29. UVM Support
29.1. Show UVM Sequence Tree
30. Scripts
30.1. dvt_code.sh
30.1.1. dvt_code.sh Syntax
30.1.2. dvt_code.sh Examples
30.2. dvt_ls.sh
30.2.1. dvt_ls.sh Syntax
30.2.2. dvt_ls.sh Examples
31. Custom Scripts
32. SCM Checkout Hook
33. Application Notes
33.1. Flow Integration
33.2. Environment Variables
33.3. Encrypted VIP Support
33.4. FPGA Support
33.4.1. Intel(Altera) Quartus
33.4.2. Xilinx ISE/Vivado
34. What is New?
35. How to Report an Issue?
36. Legal Notices
37. Third Party Licenses
38. Q & A
38.1. Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?