DVT IDE for VS Code SystemVerilog User Guide
Rev. 23.2.28, 28 November 2023

19.3 Vertical Alignment

When enabled, this option performs vertical alignment.

  • Vertical Alignment Tokens

The lines of code inside the same scope are aligned by the specified list of vertical alignment tokens. Vertical alignment is performed left to right, by the same token. For example assuming '=' and ':' as vertical align tokens: In order to use the comma character ',' as a vertical alignment token, the character must be preceded by the escaping character '\'.

Before After (":" token)
  • Only Consecutive Lines - Controls whether vertical alignment is applied only to consecutive lines.

Before After
  • Vertical Align Single Line Comments - Controls whether single line comments are vertically aligned.

Before After
  • Vertical Align To Open Parenthesis - Controls whether to vertically align relative to open parenthesis.

Before After
  • Vertical Align To Open Curly - Controls whether to vertically align relative to open curly.

Before After
  • Independent Preprocessing Scopes - Controls whether preprocessing scopes create independent alignment scopes:

Before After
  • Vertical Align Patterns - By Name Port Connections - Controls whether to align instance port connections by name:

Before After
  • Vertical Align Patterns - Class Declarations - Controls whether to align class parameters:

Before After
  • Vertical Align Patterns - Class Variable Declarations - Controls whether to align class variables:

Before After
  • Vertical Align Patterns - `defines - Controls whether to align `defines:

Before After
  • Vertical Align Patterns - Function Declarations - Controls whether to align function and task declarations:

Before After
  • Vertical Align Patterns - Function Variable Declarations - Controls whether to align function and task variable declarations:

Before After
  • Vertical Align Patterns - Interface Port Declarations - Controls whether to align interface ports:

Before After
  • Vertical Align Patterns - Interface Signal Declarations - Controls whether to align interface signals:

Before After
  • Vertical Align Patterns - Module Port Declarations - Controls whether to align module ports:

Before After
  • Vertical Align Patterns - Module Signal Declarations - Controls whether to align module signals:

Before After
  • Vertical Align Patterns - `xvm_field macros - Controls whether to align `xvm_field factory registration macros:

Before After