DVT IDE for VS Code SystemVerilog User Guide
Rev. 24.1.3, 13 February 2024

19.6 Preferences Keys

Formatting preferences are serialized as key-value pairs, by default under $HOME/.config/Code/User/settings.json.

Furthermore, an input file with the same format is used to configure Verissimo formatting rules, such as SVTB1.0.

Preference Name Details Preference Key Default Value
Whitespace    
Add Whitespace AfterList of tokens after which whitespace will be added.DVT.textEditor.systemVerilog.formatting.whitespace.addWhitespaceAfter[]
Add Whitespace BeforeList of tokens before which whitespace will be added.DVT.textEditor.systemVerilog.formatting.whitespace.addWhitespaceBefore[]
Compact Whitespace GroupsControls whether to compact consecutive whitespace characters.DVT.textEditor.systemVerilog.formatting.whitespace.compactWhitespaceGroupsfalse
Compact Consecutive Empty LinesControls whether to compact consecutive empty lines.DVT.textEditor.systemVerilog.formatting.whitespace.compactConsecutiveEmptyLinesfalse
Maximum Number Of Consecutive Empty LinesMaximum number of consecutive empty lines that can appear in a file.DVT.textEditor.systemVerilog.formatting.whitespace.maximumNumberOfConsecutiveEmptyLines1
Insert spacesWhen enabled, indentation will use space characters, otherwise tabs will be used.editor.insertSpacestrue
Remove New Line AfterList of tokens after which new lines will be removed.DVT.textEditor.systemVerilog.formatting.whitespace.removeNewLineAfter[]
Remove New Line BeforeList of tokens before which new lines will be removed.DVT.textEditor.systemVerilog.formatting.whitespace.removeNewLineBefore[]
Tab widthControls the size of a tab in spaces.editor.tabSize4
Trim End of Line WhitespaceControls whether to trim end of line whitespaces.DVT.textEditor.systemVerilog.formatting.whitespace.trimEndOfLineWhitespacetrue
Trim Whitespace LinesControls whether to trim lines containing only whitespaces.DVT.textEditor.systemVerilog.formatting.whitespace.trimWhitespaceLinestrue
Indentation    
Add New Line After Begin And Before EndControls whether to add a new line after `begin` and before `end`.DVT.textEditor.systemVerilog.formatting.indentation.addNewLineAfterBeginAndBeforeEndfalse
Add New Line After EndControls whether to add a new line after `end`.DVT.textEditor.systemVerilog.formatting.indentation.addNewLineAfterEndfalse
Close Scope MacrosList of macros that close a scope and decrease the indentation of subsequent code.DVT.textEditor.systemVerilog.formatting.indentation.closeScopeMacros[]
Do Not Indent Single Line Comments At Beginning Of LineControls whether to indent single line comments starting at the beginning of a line.DVT.textEditor.systemVerilog.formatting.indentation.doNotIndentSingleLineCommentsAtBeginningOfLinetrue
Do Not Indent Multi-line Macro DefinitionsControls whether to indent multi-line macro definitions.DVT.textEditor.systemVerilog.formatting.indentation.doNotIndentMulti-lineMacroDefinitionsfalse
ElseControls the placement of `else`: Leave as is, On a new line, On the same line. DVT.textEditor.systemVerilog.formatting.indentation.else"Leave as is"
Enable More Parameters Per Line If Less ThanControls whether to place parameters on the same line when their number does not exceed a certain value and the Parameters preference is set to One per line (open parenthesis on the same line) or One per line (open parenthesis on the next line). DVT.textEditor.systemVerilog.formatting.indentation.enableMoreParametersPerLineIfLessThanfalse
Ignore Lines Starting WithList of line prefixes matching lines that will be ignored while indenting.DVT.textEditor.systemVerilog.formatting.indentation.ignoreLinesStartingWith[]
Implicit Semi MacrosList of macros encapsulating *semicolon* or *end* delimiters.DVT.textEditor.systemVerilog.formatting.indentation.implicitSemiMacros 
Indent Multi-line AssignsControls whether to indent multi-line assigns.DVT.textEditor.systemVerilog.formatting.indentation.indentMulti-lineAssignstrue
Indent Multi Line CommentsControls whether to indent multi-line comments.DVT.textEditor.systemVerilog.formatting.indentation.indentMultiLineCommentstrue
More Parameters Per Line If Less ThanMaximum number of parameters that can appear on a line when Enable More Parameters Per Line If Less Than is enabled. DVT.textEditor.systemVerilog.formatting.indentation.moreParametersPerLineIfLessThan5
No Indent KeywordsSelection of language keywords that will not increase indentation.DVT.textEditor.systemVerilog.formatting.indentation.noIndentKeywords 
Open Scope MacrosList of macros that open a scope and increase the indentation of subsequent code.DVT.textEditor.systemVerilog.formatting.indentation.openScopeMacros[]
Optional BeginControls the placement of optional `begin`: Leave as is, On a new line, On the same line, On a new line and indent. DVT.textEditor.systemVerilog.formatting.indentation.optionalBegin"Leave as is"
ParametersControls the placement of module ports and parameters, function and task arguments, class parameters: Leave as is, One per line (open parenthesis on the same line). One per line (open parenthesis on the next line), More per line. DVT.textEditor.systemVerilog.formatting.indentation.parameters"Leave as is"
PreprocessingControls the indentation of preprocessing blocks: Leave as is, Indent, Indent and increase indentation level, Indent and increase indentation level except first, Move at first column. DVT.textEditor.systemVerilog.formatting.indentation.preprocessing"Leave as is"
Vertical Alignment    
Enable Vertical AlignControls whether to enable vertical alignment.DVT.textEditor.systemVerilog.formatting.verticalAlignment.enableVerticalAlignmentfalse
Independent Preprocessing ScopesControls whether preprocessing scopes create independent alignment scopes.DVT.textEditor.systemVerilog.formatting.verticalAlignment.independentPreprocessingScopesfalse
Only Consecutive LinesControls whether vertical alignment is applied only to consecutive lines.DVT.textEditor.systemVerilog.formatting.verticalAlignment.onlyConsecutiveLinesfalse
Vertical Align PatternsSelection of additional code patterns for which vertical alignment is enabled: By Name Port Connections, Class Declarations, Class Variable Declarations, `defines, Function Declarations, Function Variable Declarations, DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignPatterns 
Vertical Align Single Line CommentsControls whether single line comments are vertically aligned.DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignSingleLineCommentsfalse
Vertical Align To Open CurlyControls whether to vertically align relative to open curly.DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignToOpenCurlyfalse
Vertical Align To Open ParenthesisControls whether to vertically align relative to open parenthesis.DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignToOpenParenthesisfalse
Vertical Alignment TokensList of tokens used for splitting lines in the same scope in vertically aligned columns.DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignTokens "<="
Line Wrapping    
Enable Line WrappingControls whether to enable line wrapping.DVT.textEditor.systemVerilog.formatting.lineWrapping.enableLineWrappingfalse
Line WidthNumber of characters on a line after wrapping the line.DVT.textEditor.systemVerilog.formatting.lineWrapping.lineWidth80
Wrap Multi Line CommentsControls whether multi-line comments are wrapped.DVT.textEditor.systemVerilog.formatting.lineWrapping.wrapMultiLineCommentsfalse
Wrap Single Line CommentsControls whether single line comments are wrapped and moved above the code.DVT.textEditor.systemVerilog.formatting.lineWrapping.wrapSingleLineCommentsfalse