DVT IDE for VS Code SystemVerilog User Guide
Rev. 22.1.23, 16 August 2022

Chapter 18. Code Factory

The Code Factory allows you to easily generate instances, signals, and testbenches starting with modules or entities.

Factory Input

It is required that you first set an input. Place the cursor on a SystemVerilog module, interface, program, checker, or a VHDL entity definition and use the "DVT: Set Code Factory Input" command.

The current input persists until it is cleared ( "DVT: Clear Code Factory Input" command) or until a new one is set. Invoking a full build will also clear the current input.

Creating Code

Having set an input, you can use the "Trigger Suggest" command in order to do one of the following:

  • Create Instance for instantiating the design element

  • Create Signals for listing the ports of the design element as signals

  • Create Testbench for defining a testbench that instantiates the design element with all the required port connections already made

  • Create Component for defining a component (VHDL only)

The code will be inserted at the cursor's current position.

Any information or errors during Code Factory operations are shown via notifications.

Note: Cross language operations are not supported. You can't set a SystemVerilog module as input and use it in VHDL for creating output and vice-versa.