DVT VHDL IDE User Guide
Rev. 19.1.28, 14 August 2019

33.2.1 Intel(Altera) Quartus

Use the New DVT Project Wizard (menu File > New > DVT Project) to create a DVT project in the same location as an existing Quartus project. All source files and settings defined in the Quartus project configuration files will be automatically recognized.

If you want to create a DVT project in a different location from your Quartus project location you must tune the .dvt/default.build file:

+dvt_init_auto
# Note that the compilation root must be specified after the +dvt_init_auto directive
+dvt_compilation_root+/quartus/project/location

Implementation Note: Quartus projects are automatically recognized by the DVT build auto-configuration engine. For more details, see Auto-config. When the auto-configuration algorithm detects a Quartus project layout, it scans the existing Quartus project configuration files and automatically generates an equivalent DVT build configuration file (for example default.build.auto.1).

Note: The New DVT Project Wizard automatically adds both Verilog and VHDL natures. You can manually adjust this setting.

Intel(Altera) Quartus Auto-config Specific Directives

Directive Description
+dvt_autoconfig_quartus_project_revision+<revision_name>Use <revision_name>.
+dvt_autoconfig_quartus_script_location+<script_file_path>For debugging purposes. Use <script_file_path> to analyze Quartus project configuration files.
+dvt_autoconfig_disable_quartusIgnore Quartus project configuration files and fallback to default auto-config.

33.2.1.1 Intel(Altera) Quartus Libraries Compilation

In order to compile Intel(Altera) Quartus libraries:

  • specify the required libraries using the +dvt_init_altera directive

  • specify the Quartus installation path, unless $QUARTUS_ROOTDIR system variable is set

For example:

+dvt_init_altera+ALTERA+ALTERA_MF
+dvt_setenv+QUARTUS_ROOTDIR=/apps/altera/13.0sp1/quartus

The available VHDL libraries are ALTERA_MF, ALTERA, ALTERA_LNSIM, LPM, MAX, MAXII, MAXV, STRATIX, STRATIXII, STRATIXIIGX, HARDCOPYII, HARDCOPYIII, HARDCOPYIV, CYCLONE, CYCLONEII, CYCLONEIII, CYCLONEIIILS, SGATE, STRATIXGX, ALTGXB, STRATIXGX_GXB, STRATIXIIGX_HSSI, ARRIAGX_HSSI, ARRIAII, ARRIAII_HSSI, ARRIAII_PCIE_HIP, ARRIAIIGZ, ARRIAIIGZ_HSSI, ARRIAIIGZ_PCIE_HIP, ARRIAGX, STRATIXIII, STRATIXIV, STRATIXIV_HSSI, STRATIXIV_PCIE_HIP, CYCLONEIV, CYCLONEIV_HSSI, CYCLONEIV_PCIE_HIP, CYCLONEIVE, HARDCOPYIV_HSSI, HARDCOPYIV_PCIE_HIP, STRATIXV, STRATIXV_HSSI, STRATIXV_PCIE_HIP, ARRIAVGZ, ARRIAVGZ_HSSI, ARRIAVGZ_PCIE_HIP, ARRIAV, CYCLONEV.

The available Verilog libraries are ALTERA_MF_VER, ALTERA_VER, ALTERA_LNSIM_VER, LPM_VER, MAX_VER, MAXII_VER, MAXV_VER, STRATIX_VER, STRATIXII_VER, STRATIXIIGX_VER, ARRIAGX_VER, HARDCOPYII_VER, HARDCOPYIII_VER, HARDCOPYIV_VER, CYCLONE_VER, CYCLONEII_VER, CYCLONEIII_VER, CYCLONEIIILS_VER, SGATE_VER, STRATIXGX_VER, ALTGXB_VER, STRATIXGX_GXB_VER, STRATIXIIGX_HSSI_VER, ARRIAGX_HSSI_VER, ARRIAII_VER, ARRIAII_HSSI_VER, ARRIAII_PCIE_HIP_VER, ARRIAIIGZ_VER, ARRIAIIGZ_HSSI_VER, ARRIAIIGZ_PCIE_HIP_VER, STRATIXIII_VER, STRATIXIV_VER, STRATIXIV_HSSI_VER, STRATIXIV_PCIE_HIP_VER, STRATIXV_VER, STRATIXV_HSSI_VER, STRATIXV_PCIE_HIP_VER, ARRIAVGZ_VER, ARRIAVGZ_HSSI_VER, ARRIAVGZ_PCIE_HIP_VER, ARRIAV_VER, ARRIAV_HSSI_VER, ARRIAV_PCIE_HIP_VER, CYCLONEV_VER, CYCLONEV_HSSI_VER, CYCLONEV_PCIE_HIP_VER, CYCLONEIV_VER, CYCLONEIV_HSSI_VER, CYCLONEIV_PCIE_HIP_VER, CYCLONEIVE_VER, HARDCOPYIV_HSSI_VER, HARDCOPYIV_PCIE_HIP_VER.