DVT VHDL IDE User Guide
Rev. 24.1.7, 9 April 2024

12.4 Vertical Alignment

When enabled, this option performs vertical alignment.

  • Vertical Alignment Tokens (ro.amiq.vhdldt/format.vertical_align.tokens)

The lines of code inside the same scope are aligned by the specified comma separated list of vertical alignment tokens. Vertical alignment is performed left to right, by the same token. In order to use the comma character ',' as a vertical alignment token, the character must be preceded by the escaping character '\'.

Before After (":=,:" tokens)
  • Only consecutive lines (ro.amiq.vhdldt/format.vertical_align.consecutive_lines) - When enabled, only consecutive lines are vertically aligned. Two lines are consecutive if they follow each other or are separated by comment lines.

Before After
  • Vertical align single line comments (ro.amiq.vhdldt/format.vertical_align.sl_comments) - When enabled, single line comments are aligned.

Before After
  • Vertical align to open parenthesis (ro.amiq.vhdldt/format.vertical_align.paren) - When enabled, vertical align to open parenthesis.

Before After
  • Vertical Align Patterns (ro.amiq.vhdldt/format.vertical_align.vregex) :

Constant Declarations (VhdlConstantDeclarations) - Controls whether to align constant declarations.

Before After

Port Declarations (VhdlPortDeclarations) - Controls whether to align port declarations.

Before After

Record Declarations (VhdlRecordDeclarations) - Controls whether to align record declarations.

Before After

Signal Declarations (VhdlSignalDeclarations) - Controls whether to align signal declarations.

Before After

Variable Declarations (VhdlVariableDeclarations) - Controls whether to align variable declarations.

Before After

Variable, Signal, Constant Declarations (VhdlVariableSignalConstantDeclarations) - Controls whether to align variable, signal and constant declarations.

Before After