Macros
Name |
Type |
Value |
Description |
|---|---|---|---|
AE_BIT |
defined |
2 |
|
ARB_IDLE |
defined |
3'b000 |
|
ARB_RX |
defined |
3'b010 |
|
ARB_RX_DS |
defined |
3'b100 |
|
ARB_S0 |
defined |
3'b001 |
|
ARB_TX |
defined |
3'b011 |
|
ARB_TX_DS |
defined |
3'b101 |
|
ARB_TX_UPD |
defined |
3'b110 |
|
BF_BIT |
defined |
9 |
|
BK_DONE |
defined |
1'b1 |
Backoff DONE state (wait slot_cnt tobe equal bk_ended value) |
BK_IDLE |
defined |
1'b0 |
Backoff IDLE state (wait for pi_bk_start command) |
CC_BIT |
defined |
5:2 |
|
CDID_DEVICE_TYPE |
defined |
16'h3030 |
|
CE_BIT |
defined |
1 |
|
CFID_MAC_ID |
defined |
16'h1010 |
|
CFID_MANUFACTURER_ID |
defined |
16'h2020 |
|
DATA |
defined |
3'h7 |
|
DATA_DROP |
defined |
3'h2 |
|
DATA_READ |
defined |
3'h1 |
|
DEVADDR |
defined |
3'h4 |
|
DE_BIT |
defined |
0 |
|
EC_BIT |
defined |
6 |
|
EF_BIT |
defined |
4 |
|
EMAC_10_100_MBPS |
ifdef |
||
ERROR_LENGTH |
defined |
8'h04 |
|
FC_DEST_ADDR |
defined |
48'h0180C2000001 |
Control frame destination address |
FC_IDLE |
defined |
2'd0 |
FSM states encoding (flow control frame FSM) |
FC_OP_TYPE |
defined |
2'd1 |
|
FC_READ |
defined |
3'h4 |
|
FC_TIME_VAL |
defined |
2'd2 |
|
FC_WAIT_64 |
defined |
2'd3 |
|
FL_BIT |
defined |
22:8 |
Statistic word bits |
HASH |
defined |
3'd2 |
|
HOST_NOP |
defined |
2'b00 |
|
HOST_READ |
defined |
2'b10 |
HOST bus interface operations |
HOST_WRITE |
defined |
2'b01 |
|
IDLE |
defined |
3'd0 |
|
LC_BIT |
defined |
7 |
|
LE_BIT |
defined |
3 |
|
LP_BIT |
defined |
7 |
|
MATCH_1 |
defined |
3'd3 |
|
MATCH_2 |
defined |
3'd4 |
|
MF_BIT |
defined |
6 |
|
MULTICAST_BIT |
defined |
40 |
Global multicast bit (see 802.3-2002_part2.pdf, 22.2.3 Frame structure) |
OF_BIT |
defined |
0 |
|
OPCODE |
defined |
3'h3 |
|
PREAMBLE |
defined |
3'h1 |
|
REGADDR |
defined |
3'h5 |
|
REGS_HWRITE |
defined |
3'b100 |
|
REGS_IDLE |
defined |
3'b000 |
|
REGS_READ |
defined |
3'b010 |
|
REGS_WRITE |
defined |
3'b001 |
|
RX_CRC_CHECK |
defined |
32'hC704DD7B |
CRC check value |
RX_DA |
defined |
4'h3 |
|
RX_DATA_0 |
defined |
4'h6 |
|
RX_DATA_1 |
defined |
4'h7 |
|
RX_DS_IDLE |
defined |
3'b000 |
RX ds aquire state values |
RX_DS_MAIN |
defined |
3'b001 |
|
RX_DS_READ |
defined |
3'b010 |
|
RX_DS_SUSPEND |
defined |
3'b011 |
|
RX_DS_WAIT |
defined |
3'b100 |
|
RX_ERROR_DATA |
defined |
8'h1f |
|
RX_EXTEND |
defined |
4'h8 |
|
RX_EXTEND_DATA |
defined |
8'h0f |
|
RX_FCOPTYPE_CHECK_0 |
defined |
8'h88 |
FC frame opcode |
RX_FCOPTYPE_CHECK_1 |
defined |
8'h08 |
|
RX_FCOPTYPE_CHECK_2 |
defined |
8'h00 |
|
RX_FCOPTYPE_CHECK_3 |
defined |
8'h01 |
|
RX_IDLE |
defined |
4'h0 |
FSM states encoding (receive frame) |
RX_PREAMBLE |
defined |
4'h1 |
|
RX_PREAMBLE_DATA |
defined |
4'h5 |
GMII Data encoding |
RX_READ_DS |
defined |
3'b001 |
|
RX_SA |
defined |
4'h4 |
|
RX_SFD |
defined |
4'h2 |
|
RX_SFD_DATA |
defined |
4'hd |
|
RX_STAT |
defined |
3'b101 |
|
RX_TYPE |
defined |
4'h5 |
|
RX_WAIT |
defined |
4'h9 |
|
RX_WRITE |
defined |
3'b011 |
|
RX_WRITE_DS |
defined |
3'b110 |
|
RX_WRITE_PAUSE |
defined |
3'b010 |
|
SIMULATION_VALUE_REDUCED |
ifdef |
synopsys translate_off Reduced 512 time slot (for simulation) |
|
SPLIT_IDLE |
defined |
3'h0 |
FSM states encoding |
SPLIT_WAIT |
defined |
3'h3 |
|
START |
defined |
3'h2 |
|
TJ_BIT |
defined |
8 |
|
TL_BIT |
defined |
5 |
|
TP |
defined |
1 |
Delay assertion output signals |
TURNAR |
defined |
3'h6 |
|
TX_BACKOFF |
defined |
4'h8 |
|
TX_BEGIN |
defined |
4'd0 |
****************************************************************** Transmit IFG initialize after reset (only) |
TX_CARRIER |
defined |
4'd7 |
Carrier monitor (after remote transmit) |
TX_CRC |
defined |
4'h6 |
|
TX_CRS_ERR |
defined |
4'hd |
|
TX_CRS_JAM |
defined |
4'hc |
|
TX_DATA |
defined |
4'h4 |
|
TX_DEFER |
defined |
4'h1 |
|
TX_DS_IDLE |
defined |
3'b000 |
TX ds aquire state values |
TX_DS_MAIN |
defined |
3'b001 |
|
TX_DS_READ |
defined |
3'b010 |
|
TX_DS_SUSPEND |
defined |
3'b011 |
|
TX_DS_UPD_IDLE |
defined |
2'b00 |
|
TX_DS_UPD_WRITE |
defined |
2'b01 |
|
TX_DS_WAIT |
defined |
3'b100 |
|
TX_ERROR |
defined |
4'd3 |
Collision during carrier extend phase |
TX_ERROR_DATA |
defined |
8'h1f |
|
TX_EXTEND |
defined |
4'h9 |
|
TX_EXTEND_DATA |
defined |
4'hf |
|
TX_IDLE |
defined |
4'd1 |
Transmit enable |
TX_IDLE_DATA |
defined |
8'h00 |
|
TX_IFG1 |
defined |
4'd5 |
IFG1 (ignore the carrier sense assertion) |
TX_IFG2 |
defined |
4'd6 |
IFG2 (ignore the carrier sense assertion) |
TX_JAM |
defined |
4'd2 |
Collision during data phase |
TX_JAM_DATA |
defined |
4'hf |
|
TX_JAM_NIBBLE |
defined |
4'hf |
|
TX_LATENCY |
defined |
4'd8 |
MAC latency 2 cycles |
TX_LW_BUFF |
defined |
4'b1000 |
|
TX_LW_BURST |
defined |
4'b1001 |
|
TX_LW_DS |
defined |
4'b0111 |
|
TX_LW_FRM |
defined |
4'b0110 |
|
TX_MAC_JABBER_WORDS_LIMIT |
defined |
16'h1001 |
|
TX_PAD |
defined |
4'h5 |
|
TX_PAD_DATA |
defined |
4'h0 |
|
TX_PREAMBLE |
defined |
4'h2 |
|
TX_PREAMBLE_DATA |
defined |
4'h5 |
|
TX_READ |
defined |
4'b0011 |
|
TX_READ_DS |
defined |
4'b0001 |
|
TX_READ_PAUSE |
defined |
4'b0010 |
|
TX_SFD |
defined |
4'h3 |
|
TX_SFD_DATA |
defined |
4'hd |
|
TX_STOP |
defined |
4'hb |
|
TX_UPD_FIFO_RANGE |
defined |
3 |
range of the tx descriptor update fifo =log2(TX_UPD_FIFO_SIZE) |
TX_UPD_FIFO_SIZE |
defined |
8 |
size of the tx descriptor update fifo |
TX_UPD_WAIT |
defined |
4'b0101 |
|
TX_WAIT |
defined |
4'd4 |
Wait carrier to be deasserted after own transmit |
TX_WRITE_DS |
defined |
4'b0100 |
|
UF_BIT |
defined |
1 |
|
WAIT |
defined |
3'd1 |
|
WRITE_1 |
defined |
3'd1 |
Write table (write odd word) |
WRITE_2 |
defined |
3'd2 |
and exact address match 16-bits (when last Hash + 1 Exact Address Match) Write table exact address match 16-bits (1 Exact Address Match) |
WRITE_3 |
defined |
3'd3 |
Write table exact address match 16-bits (1 Exact Address Match) |
WRITE_4 |
defined |
3'd4 |
Write table exact address match 16-bits (1 Exact Address Match) |
WR_DATA |
defined |
3'd1 |
|
WR_EXTEND |
defined |
3'd4 |
|
WR_IDLE |
defined |
3'd0 |
FSM states encoding (memory write FSM) |
WR_OVERRUN |
defined |
3'd2 |
|
WR_STAT |
defined |
3'd3 |
ARBITER states