Module ip_mac_rx_gmii_g

Block Diagram of ip_mac_rx_gmii_g

Overview

The EMAC Receive MII/GMII module is responsible to multiplex the MII input interface (nibble oriented) signals coming from physical layer into GMII format when 10/100 Mbps operating mode is selected or to pass the GMII signal to the EMAC Receive State Machine when operating speed above 100 Mbps.

The EMAC Receive MII/GMII module it also checks for invalid Ethernet MAC frames by checking for proper byte-boundary alignment of the end of the frame. The block is responsible to generate the alignment error indication when frame length is not an integer number of bytes.

The module is also responsible for the internal loop-back operation, when the EMAC operates in loop-back mode. The EMAC Clock Manager module is responsible to switch between the input receive clock and transmit clock for loop-back operation.

Ports
Name	Direction	Type	Description
pi_loopback	input	wire logic	Loopback mode select
pi_tx_gmii_val	input	wire logic	Loopback Info Loopback MII/GMII data valid indication (from TX)
pi_tx_gmii_err	input	wire logic	Loopback MII/GMII error indication (from TX)
pi_tx_gmii_data	input	wire logic[7:0]	Loopback MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from TX)
pi_gmii_val	input	wire logic	gmii Data Valid, Data Input Signals and Alignment Error Receive MII/GMII data valid indication (from PHY)
pi_gmii_data	input	wire logic[7:0]	Receive MII/GMII error indication (from PHY)
pi_gmii_err	input	wire logic	Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY)
po_gmii_val	output	wire logic	GMII Data Valid, Data Input Signals and Alignment Error Receive MII/GMII data valid indication (to RX state)
po_gmii_data	output	wire logic[7:0]	Receive MII/GMII error indication (to RX state)
po_gmii_err	output	wire logic	Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (to RX state)

Instances

ip_emac_topip_emac_top
- mac_topip_mac_top_g
  
  mac_rx_topip_mac_rx_top_g
  
  rx_gmii