Module ip_mac_tx_sync_g
Block Diagram of ip_mac_tx_sync_g
Overview
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_tx_reset |
input |
wire logic |
Transmit clock and reset Global Hardware/Software reset (transmit clock domain, active low) |
pi_tx_f_clock |
input |
wire logic |
Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_host_idone |
output |
var reg |
Reset done Transmit initialization done (host clock domain) |
pi_host_reset |
input |
wire logic |
Host clock and reset Global Hardware/Software reset (host clock domain, active low) |
pi_host_clock |
input |
wire logic |
Host clock (from Clock Manager) |
pi_tx_stop |
input |
wire logic |
Inputs -> Synchronized outputs Transmit stop command acknowledge (transmit clock domain) |
po_host_stop |
output |
var reg |
Transmit stop command acknowledge (synchronized to host clock domain) |
pi_host_stop |
input |
wire logic |
Transmit stop command (host clock domain) |
po_tx_stop |
output |
var reg |
Transmit stop command (synchronized to transmit clock domain) |
pi_rx_fc_tx_off |
input |
wire logic |
Received transmit off command (receive clock domain) |
po_tx_fc_tx_off |
output |
var reg |
Transmit off command (synchronized to transmit clock domain) |
pi_rx_fc_xoff |
input |
wire logic |
Receive FIFO level exceed high threshold, XOFF FC packet insert (receive clock domain) |
pi_rx_fc_xon |
input |
wire logic |
Transmit XOFF FC packet insert (synchronized to transmit clock domain) |
po_tx_fc_xoff |
output |
var reg |
Receive FIFO level below low threshold, XON FC packet insert (receive clock domain) |
po_tx_fc_xon |
output |
var reg |
Transmit XON FC packet insert (synchronized to transmit clock domain) |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_tx_topip_mac_tx_top_g
tx_sync
The EMAC Transmit Synchronization module is responsible to synchronize all the control signals necessary to control the functionality of the transmit clock domain modules. Also the signals generated by the transmit modules and needed by the host clock domain modules are synchronized by the EMAC Transmit Synchronization module to host clock domain. In order to avoid the metastability of the output signal the synchronization from one clock domain to another will require two DFF's. The host and transmit clocks used by the synchronization module are free running clocks, since there is no possibility to generate synchronous wake-up's signals for gated clock module. Also this module is responsible to synchronize the reset done information (initialization done) used by the host DMA module in order to start data transfers.