Module ip_mac_tx_top_g
Name |
Default value |
Description |
---|---|---|
TX_MEM_ADDR |
9 |
Name |
Direction |
Type |
Description |
---|---|---|---|
pi_tx_reset |
input |
wire logic |
Global Software/Hardware Reset (transmit clock domain) |
pi_host_reset |
input |
wire logic |
Global Software/Hardware Reset (host clock domain) |
pi_tx_f_clock |
input |
wire logic |
Transmit clock Free Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_tx_g_clock |
input |
wire logic[3:0] |
Gated Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_tx_en_clock |
output |
wire logic[3:0] |
Enable Transmit GMII/MII 125/25/2.5 MHz clock gated clock enable |
po_host_init_done |
output |
wire logic |
Initialisation done Transmit initialisation done (host clock domain) |
pi_host_stop_xmit |
input |
wire logic |
Start/Stop transmit process Transmit EMAC stop command |
po_host_stop_xmit |
output |
wire logic |
Transmit EMAC stopped |
pi_rx_fc_xoff_tgl |
input |
wire logic |
Configuration Interface |
pi_rx_fc_xon_tgl |
input |
wire logic |
from RX EMAC insert XON flow control information |
pi_tx_xoff_value |
input |
wire logic[15:0] |
from configuration XOFF flow control pause value |
pi_tx_xon_value |
input |
wire logic[15:0] |
from configuration XON flow control pause value |
pi_tx_col_limit |
input |
wire logic[4:0] |
Half Duplex back presure collision limit |
pi_tx_fc_enable |
input |
wire logic |
(maximum collision number during back presure algorithm) Transmit flow control enable |
pi_rx_fc_tx_off |
input |
wire logic |
Flow control Stop transmit commang (flow control received) |
pi_tx_gigabit |
input |
wire logic |
Operating 1000 Mbps (Gigabit) mode |
pi_tx_burst_lim |
input |
wire logic[15:0] |
Burst limit (valid only when operating mode is 1000 Mbps) |
pi_tx_burst_en |
input |
wire logic |
Burst enable (valid only when operating mode is 1000 Mbps) |
pi_tx_half_duplex |
input |
wire logic |
Operating Half Duplex mode |
pi_tx_ifg_cfg_1 |
input |
wire logic[7:0] |
Interframe gap part 1 (usualy 2/3 from IFG) |
pi_tx_ifg_cfg_2 |
input |
wire logic[7:0] |
Interframe gap part 2 (usualy 1/3 from IFG) |
pi_tx_store_fwd |
input |
wire logic |
Store and Forward transmit FIFO operating mode |
pi_tx_threshold |
input |
wire logic[TX_MEM_ADDR-1:0] |
Cut Trough (pi_emac_store_fwd not asserted) FIFO threshold |
po_tx_xmit_nfc |
output |
wire logic |
GMII/MII interface |
po_gmii_en |
output |
wire logic |
NOTE: This signal is not asserted during flow control frame transmission Transmit MII/GMII enable indication (to PHY) |
po_gmii_err |
output |
wire logic |
Transmit MII/GMII error indication (to PHY) |
po_gmii_data |
output |
wire logic[7:0] |
Transmit MII/GMII data (MII data is po_emac_tx_data[3:0]) (to PHY) |
pi_gmii_col |
input |
wire logic |
Collision indication (from PHY) |
pi_gmii_crs |
input |
wire logic |
Carrier Sense indication (from PHY) |
pi_host_stat_read |
input |
wire logic |
Read statistic word command |
po_host_stat_empty |
output |
wire logic |
Statistic FIFO not empty |
po_host_stat_last |
output |
wire logic |
Last statistic word indication |
po_host_stat_data |
output |
wire logic[9:0] |
Statistic TDES0 word data |
pi_host_clock |
input |
wire logic |
HOST interface |
pi_host_little |
input |
wire logic |
Little endian (data path organisation) |
pi_host_enable_wr |
input |
wire logic |
Transmit MAC data path, HOST enable command |
po_host_full_wr |
output |
wire logic |
Transmit MAC data path, HOST FIFO full indication |
po_host_last_wr |
output |
wire logic |
Transmit MAC data path, HOST FIFO last location indication |
pi_host_data_wr |
input |
wire logic[31:0] |
Transmit MAC data path, HOST data (transmit data) |
pi_host_byte_wr |
input |
wire logic[1:0] |
Transmit MAC data path, HOST byte enable (transmit data byte enable) |
pi_host_start_wr |
input |
wire logic |
Transmit MAC data path, HOST start of frame indication |
pi_host_end_wr |
input |
wire logic |
Transmit MAC data path, HOST start of frame indication |
pi_host_error_wr |
input |
wire logic |
Unused please check if useful (if not remove) |
pi_host_pad_wr |
input |
wire logic |
Transmit MAC data path, HOST padding enable (valid only when pi_host_end_wr) |
pi_host_crc_wr |
input |
wire logic |
Transmit MAC data path, HOST crc enable (valid only when pi_host_end_wr) |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
mac_tx_top : ip_mac_tx_top_g#(.TX_MEM_ADDR(10))
Submodules
- ip_mac_tx_top_g#(.TX_MEM_ADDR(10))
tx_bkoff : ip_mac_tx_bkoff_g
tx_data_async : ip_async_fifo_g #(.MEM_WIDTH(39))
tx_data_dram : ip_mac_dram_001 #(.MEM_ADDR(10), .MEM_WIDTH(39))
tx_dpath : ip_mac_tx_dpath_g
tx_dsplit : ip_mac_tx_dsplit_g #(.MEM_ADDR(10))
tx_endian : ip_mac_big_endian
tx_fc_gen : ip_mac_fc_gen_g
tx_fifo : ip_mac_tx_fifo_g #(.MEM_ADDR(10))
tx_fsm : ip_mac_tx_fsm_g
tx_gmii : ip_mac_tx_gmii_g
tx_stat_async : ip_async_fifo_g #(.MEM_WIDTH(10))
tx_sync : ip_mac_tx_sync_g
Transmit memory address width (9 -> 512 locations, 10->1024)