Module ip_synchronous_fifo

MEM_ADDRpi_resetlogicpi_clocklogicpi_wr_enlogicpi_rd_enlogicpo_rd_addrlogic[MEM_ADDR-1:0]po_wr_addrlogic[MEM_ADDR-1:0]po_fulllogicpo_emptylogicpo_overflowlogicpo_underflowlogic

Block Diagram of ip_synchronous_fifo

Parameters

Name

Default value

Description

MEM_ADDR

6

Transmit memory address width (9 -> 512 locations, 10->1024)
Ports

Name

Direction

Type

Description

pi_reset

input

wire logic

pi_clock

input

wire logic

po_rd_addr

output

wire logic[MEM_ADDR-1:0]

po_wr_addr

output

wire logic[MEM_ADDR-1:0]

pi_wr_en

input

wire logic

pi_rd_en

input

wire logic

po_full

output

wire logic

po_empty

output

wire logic

po_overflow

output

wire logic

po_underflow

output

wire logic