Module ip_mac_hostif_tx
Block Diagram of ip_mac_hostif_tx
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_reset |
input |
wire logic |
|
pi_g_clock |
input |
wire logic |
host gated clock |
pi_g1_clock |
input |
wire logic |
host gated clock 1 |
pi_f_clock |
input |
wire logic |
host free clock |
po_en_clock |
output |
var reg |
enable clock condition |
po_en1_clock |
output |
var reg |
enable clock condition 1 |
po_tx_enable_wr |
output |
wire logic |
tx mac fifo interface rx fifo read command |
pi_tx_full |
input |
wire logic |
rx fifo full |
pi_tx_last_wr |
input |
wire logic |
rx fifo almost full |
po_tx_data |
output |
wire logic[31:0] |
rx fifo data |
po_tx_be |
output |
wire logic[1:0] |
tx fifo data byte enable |
po_tx_sof |
output |
wire logic |
tx fifo start of frame |
po_tx_eof |
output |
wire logic |
tx fifo end of frame |
po_tx_put_crc |
output |
wire logic |
put crc indication (valid only when sof=1) |
po_tx_put_padding |
output |
wire logic |
put padding indication (valid only when sof=1) |
po_tx_err |
output |
wire logic |
put error indication (valid only when eof=1) |
pi_host_sdata |
input |
wire logic[31:0] |
host interface from host interface |
pi_host_sdva |
input |
wire logic |
from host interface |
po_tx_upd_read |
output |
wire logic |
TX update fifo interface |
pi_tx_upd_empty |
input |
wire logic |
|
pi_tx_upd_last |
input |
wire logic |
|
pi_tx_upd_data |
input |
wire logic[9:0] |
|
tx_valid_ds_read |
output |
var reg |
ip_mac_hostif_txds to ip_mac_hostif_txds (new descriptor polling enabled) |
tx_ds_next_addr |
input |
wire logic[31:0] |
from ip_mac_hostif_txds (new descriptor address) |
tx_ds_addr_valid |
input |
wire logic |
from ip_mac_hostif_txds (new descriptor address valid) |
pi_tx_ds0_poll |
input |
wire logic[31:0] |
from ip_mac_hostif_txds (new descriptor address valid) |
po_tx_ds1 |
output |
wire logic[1:0] |
|
po_tx_ds3 |
output |
wire logic[31:0] |
|
tx_allowed |
input |
wire logic |
ip_mac_hostif_arb from pi_mac_hostif_arb (tx upd req allowed) |
tx_req |
output |
var reg |
request to arb from tx upd ds process |
tx_mcmd |
output |
var reg[1:0] |
tx update ds mcmd |
tx_maddr |
output |
var reg[31:0] |
tx update ds maddr |
tx_mlast |
output |
wire logic |
tx update ds mlast |
tx_frame_transmit |
output |
var reg |
to ip_mac_hostif_arb (used in arbitration process) |
tx_upd_allowed |
input |
wire logic |
from pi_mac_hostif_arb (tx upd req allowed) |
tx_upd_req |
output |
var reg |
request to arb from tx upd ds process |
tx_upd_mcmd |
output |
var reg[1:0] |
tx update ds mcmd |
tx_upd_maddr |
output |
var reg[31:0] |
tx update ds maddr |
tx_upd_mdata |
output |
var reg[31:0] |
tx update ds mdata |
tx_upd_mlast |
output |
var reg |
tx update ds mlast |
po_regs_csr5_unf |
output |
var reg |
ip_mac_regs_bank (config) transmit underflow |
po_regs_csr5_ti |
output |
var reg |
transmit frame complete (to CSR5 TI) |
po_regs_csr5_tjt |
output |
var reg |
transmit jabber timeout error |
pi_regs_csr14_st |
input |
wire logic |
start/stop transmit |
pi_config_burst_size |
input |
wire logic[5:0] |
limit for rx tx burst transfer |
Always Blocks
- always @ ( posedge pi_g1_clock or negedge pi_reset )
this process reads from both tx_upd_fifo and tx_upd_resp_fifo, constructs TX_RDS0 and assert tx_ds_req to arbiter along with address(tx_upd_fifo) and data (tx_upd_resp_fifo)
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`TX_DS_UPD_IDLE |
`TX_DS_UPD_WRITE |
[(!(~ pi_reset) && (tx_upd_req && tx_upd_allowed))] |
2 |
`TX_DS_UPD_WRITE |
`TX_DS_UPD_IDLE |
[(!(~ pi_reset) && (pi_host_sdva))] |
- always @ ( posedge pi_f_clock or negedge pi_reset )
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`TX_IDLE |
`TX_READ_DS |
[(!(~ pi_reset) && !(! pi_regs_csr14_st || ! tx_ds_addr_valid) && !(tx_ds_addr_valid && ! pi_tx_full && ! pi_tx_last_wr && ! tx_upd_fifo_full && ! tx_req) && (tx_allowed))] |
2 |
`TX_READ_DS |
`TX_READ_PAUSE |
[(!(~ pi_reset) && (pi_host_sdva) && !(tx_burst_cnt == 0) && !(tx_burst_cnt == 1) && (tx_burst_cnt == 2))] |
3 |
`TX_READ_PAUSE |
`TX_IDLE |
[(!(~ pi_reset) && (! tx_ds_valid))] |
4 |
`TX_READ_PAUSE |
`TX_READ |
[(!(~ pi_reset) && !(! tx_ds_valid) && !(! pi_tx_full && ! pi_tx_last_wr && ! tx_req) && (tx_allowed))] |
5 |
`TX_READ |
`TX_WRITE_DS |
[(!(~ pi_reset) && !(tx_allowed && pi_host_sdva) && (! tx_mlast && tx_word_remained && ! pi_tx_last_wr && ! pi_tx_full) && (tx_next_state == 4’b0100)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && !(tx_ds1[30]) && !(tx_word_remained))] |
6 |
`TX_READ |
`TX_IDLE |
[(!(~ pi_reset) && !(tx_allowed && pi_host_sdva) && (! tx_mlast && tx_word_remained && ! pi_tx_last_wr && ! pi_tx_full) && !(tx_next_state == 4’b0100) && (tx_next_state == 4’b0000)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && (tx_buff_cnt == tx_curr_buff_size - 1) && (tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && (tx_ds1[30]) && !(tx_word_remained))] |
7 |
`TX_READ |
`TX_READ_PAUSE |
[(!(~ pi_reset) && !(tx_allowed && pi_host_sdva) && (! tx_mlast && tx_word_remained && ! pi_tx_last_wr && ! pi_tx_full) && !(tx_next_state == 4’b0100) && !(tx_next_state == 4’b0000)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && !(tx_buff_cnt == tx_curr_buff_size - 1) && (tx_burst_cnt == pi_config_burst_size - 1) && !(tx_word_remained)), (!(~ pi_reset) && (tx_allowed && pi_host_sdva) && (tx_mlast1) && (tx_buff_cnt == tx_curr_buff_size - 1) && !(tx_cur_buff || tx_ds1[24] || tx_ds1[21 : 11] == 0) && !(tx_word_remained))] |
8 |
`TX_WRITE_DS |
`TX_IDLE |
[(!(~ pi_reset) && (tx_allowed && pi_host_sdva))] |
9 |
default |
`TX_IDLE |
[!(~ pi_reset)] |
Instances
- ip_emac_topip_emac_top
- host_ifip_mac_hostif_top
hostif_tx
Global interface global asynchronous pi_reset