Module ip_mac_hostif_rxds

Block Diagram of ip_mac_hostif_rxds

Ports
Name	Direction	Type	Description
pi_reset	input	wire logic	Global interface global asynchronous pi_reset
pi_g_clock	input	wire logic	host gated clock
pi_f_clock	input	wire logic	host free clock
po_en_clock	output	var reg	enable clock condition
pi_host_sdva	input	wire logic
pi_host_sdata	input	wire logic[31:0]	mapped to pi_host_sdata[31]
pi_rx_ds_allowed	input	wire logic
pi_rx_empty	input	wire logic
pi_rx_last_rd	input	wire logic
po_rx_ds_next_addr	output	var reg[31:0]	output
po_rx_ds_addr_valid	output	var reg	output
po_rx_ds_mlast	output	var reg	output
po_rx_ds_mcmd	output	var reg[1:0]	output
po_rx_ds_req	output	var reg	output
po_rx_ds_maddr	output	wire logic[31:0]	output
pi_rx_valid_ds_read	input	wire logic	input
pi_rx_ds1	input	wire logic[1:0]	holds current rx descriptor body mapped to rx, pi_rx_ds1[25:24]
pi_rx_ds3	input	wire logic[31:0]
pi_regs_csr2_rpd	input	wire logic	Registers bank interface receive poll demand
pi_regs_csr4_srl	input	wire logic[29:0]	receive descriptor base address
po_regs_csr5_ru	output	var reg	receive buffer unavailable
pi_regs_csr14_sr	input	wire logic	start / stop receive
pi_config_ds_offset	input	wire logic[4:0]	offset to increment the address if a descriptor

Always Blocks

always @ ( posedge pi_f_clock or negedge pi_reset ) 

Gated Clock Enable

FSM Transitions for rx_ds_state
#	Current State	Next State	Condition
1	`RX_DS_IDLE	`RX_DS_MAIN	[(!(~ pi_reset) && !(! pi_regs_csr14_sr))]
2	`RX_DS_MAIN	`RX_DS_READ	[(!(~ pi_reset) && (pi_rx_ds_allowed))]
3	`RX_DS_READ	`RX_DS_WAIT	[(!(~ pi_reset) && (pi_host_sdva) && (pi_host_sdata))]
4	`RX_DS_READ	`RX_DS_SUSPEND	[(!(~ pi_reset) && (pi_host_sdva) && !(pi_host_sdata))]
5	`RX_DS_WAIT	`RX_DS_MAIN	[(!(~ pi_reset) && (pi_rx_valid_ds_read))]
6	`RX_DS_SUSPEND	`RX_DS_MAIN	[(!(~ pi_reset) && (rx_mac_ds_poll \|\| pi_regs_csr2_rpd))]

Instances