Module ip_mac_tx_dpath_g

Block Diagram of ip_mac_tx_dpath_g

Ports
Name	Direction	Type	Description
pi_reset	input	wire logic	Global Software/Hardware Reset (transmit clock domain)
pi_g_clock	input	wire logic	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager)
pi_err	input	wire logic	Signals comming in from the data FIFO related to data transfer Error indication
pi_data	input	wire logic[7:0]	Data bus (frame data 8-bit word)
pi_valid	input	wire logic	Valid data
pi_mac_state	input	wire logic[3:0]	MAC state
pi_en_high	input	wire logic	Enable High (MSB)
pi_gigabit	input	wire logic	Operating 1000 Mbps (Gigabit) mode
pi_burst_en	input	wire logic	Burst enable (valid only when operating mode is 1000 Mbps)
pi_half_duplex	input	wire logic	GMII Interface Half duplex operating mode
pi_gmii_col	input	wire logic	Collision indication (from PHY)
po_gmii_en	output	var reg	Transmit MII/GMII enable indication (to PHY)
po_gmii_err	output	var reg	Transmit MII/GMII error indication (to PHY)
po_gmii_data	output	var reg[7:0]	Transmit MII/GMII data (MII data is po_emac_tx_data[3:0]) (to PHY)
po_xmit_busy	output	var reg	Used by the defering process (transmit enable ored with transmit error)

Functions

crc32_data8 ( logic[31:0] crc, logic[7:0] data ) 

CRC: 32 DATA: 8, POLY: 104C11DB7 next crc

Instances