Module ip_mac_regs_bank
Name |
Direction |
Type |
Description |
---|---|---|---|
pi_host_reset |
input |
wire logic |
|
pi_host_clock |
input |
wire logic |
host domain clock |
pi_config_mcmd |
input |
wire logic[1:0] |
host access interface |
pi_config_maddr |
input |
wire logic[31:0] |
|
pi_config_mdata |
input |
wire logic[31:0] |
|
po_config_sdva |
output |
var reg |
pi_config_mlast, |
po_config_sdata |
output |
var reg[31:0] |
|
po_config_serr |
output |
var reg |
|
pi_host_serr |
input |
wire logic |
failure on host data interface |
pi_host_base_addr |
input |
wire logic[23:0] |
internal space base address |
po_host_int |
output |
var reg |
general interrupt to the host |
po_setup_wakeup |
output |
var reg |
setup interface |
po_setup_wr_data |
output |
wire logic[31:0] |
|
po_setup_wr_setup |
output |
wire logic |
|
po_host_csr0_tap |
output |
wire logic[15:0] |
host domain register outputs & inputs |
po_host_csr0_ape |
output |
wire logic |
|
po_host_csr0_pbl |
output |
wire logic[5:0] |
|
po_host_csr0_ble |
output |
wire logic |
|
po_host_csr0_dso |
output |
wire logic[4:0] |
|
po_host_csr0_bar |
output |
wire logic |
|
po_host_csr14_swr |
output |
wire logic |
|
po_host_csr1_tpd |
output |
var reg |
transmit poll demand |
po_host_csr2_rpd |
output |
var reg |
receive poll demand |
po_host_csr3_stl |
output |
wire logic[29:0] |
transmit descriptor base address |
po_host_csr4_srl |
output |
wire logic[29:0] |
receive descriptor base address |
pi_rx_ovf |
input |
wire logic |
reveive overflow (from HOST If Rx statistic compilation) |
pi_rx_csr5_rwt |
input |
wire logic |
pi_host_csr5_ts, //transmit process state pi_host_csr5_rs, //receive process state receive watchdog timeout(16k limit) |
pi_host_csr5_rps |
input |
wire logic |
receive process stopped |
pi_host_csr5_ru |
input |
wire logic |
receive buffer unavailable |
pi_host_csr5_ri |
input |
wire logic |
receive interupt |
pi_tx_csr5_unf |
input |
wire logic |
transmit underflow (from HOST If Tx statistic compilation) |
pi_tx_csr5_tjt |
input |
wire logic |
transmit jabber time-out |
pi_host_csr5_tu |
input |
wire logic |
transmit buffer unavailable |
pi_host_csr5_tps |
input |
wire logic |
transmit process stopped |
pi_host_csr5_ti |
input |
wire logic |
transmit interrupt |
po_tx_csr6_sf |
output |
wire logic |
transmission store and forward OR transmit when threshold csr6[24:14] reached |
po_tx_csr6_tr |
output |
wire logic[10:0] |
transmission threshold |
po_global_csr6_om |
output |
wire logic[1:0] |
global operating mode (10/100/1G) |
po_global_csr6_fd |
output |
wire logic |
full-duplex mode enable |
po_global_csr6_be |
output |
wire logic |
burst enable (when 1G mode selected) |
po_rx_csr6_pm |
output |
wire logic |
receive pass all multicast enable |
po_rx_csr6_pr |
output |
wire logic |
receive promiscuous mode enable |
po_rx_csr6_perfectf |
output |
wire logic |
perfect filtering |
po_rx_csr6_hashf |
output |
wire logic |
hash filtering |
po_rx_csr6_inversef |
output |
wire logic |
inverse filtering |
po_rx_csr6_multicast_only |
output |
wire logic |
imperfect filtering |
po_rx_csr6_pb |
output |
wire logic |
receive pass bad frames |
po_mac_csr6_lb |
output |
wire logic |
loopback mode enable |
po_tx_csr8_ifg1 |
output |
wire logic[7:0] |
pi_rx_csr8_mfc_inc, // missed frame counter increment command IFG1 |
po_tx_csr8_ifg2 |
output |
wire logic[7:0] |
IFG2 |
po_tx_csr9_bl |
output |
wire logic[15:0] |
burst length |
po_tx_csr10_xon |
output |
wire logic[15:0] |
tx pause xon |
po_tx_csr10_xoff |
output |
wire logic[15:0] |
tx pause xoff |
po_rx_csr11_bcn |
output |
wire logic[5:0] |
receive backpressure collision number |
po_rx_csr11_erfc |
output |
wire logic |
receive enable flow control |
po_rx_csr11_etfc |
output |
wire logic |
transmit enable flow control |
po_rx_csr11_put |
output |
wire logic[10:0] |
pause upper threshold |
po_rx_csr11_plt |
output |
wire logic[10:0] |
pause lower threshold |
po_mdio_csr12_sb |
output |
wire logic |
MDIO start |
pi_mdio_csr12_sb |
input |
wire logic |
mdio busy |
po_mdio_csr12_rnw |
output |
wire logic |
MDIO r/w |
po_mdio_csr12_rad |
output |
wire logic[4:0] |
MDIO register address |
po_mdio_csr12_dad |
output |
wire logic[4:0] |
MDIO device address |
pi_mdio_csr13_mer |
input |
wire logic |
mdio error |
po_mdio_csr13_md |
output |
wire logic[15:0] |
MDIO write data to MDIO if |
pi_mdio_csr13_md |
input |
wire logic[15:0] |
MDIO read data from MDIO if |
po_host_csr14_sr |
output |
wire logic |
start / stop receive |
po_host_csr14_st |
output |
wire logic |
start / stop transmit |
po_tx_csr14_not_st |
output |
wire logic |
tx stop transmit |
po_tx_csr14_not_sr |
output |
wire logic |
rx stop receive |
pi_tx_idone |
input |
wire logic |
MAC tx initialization done |
pi_rx_idone |
input |
wire logic |
MAC rx initialization done |
po_global_cfda_slm |
output |
wire logic |
sleep mode enable |
po_global_cfda_szm |
output |
wire logic |
snooze mode enable |
Always Blocks
- always @ ( negedge pi_host_reset or posedge pi_host_clock )
R/W registers
# |
Current State |
Next State |
Condition |
---|---|---|---|
1 |
`REGS_IDLE |
`REGS_WRITE |
[(!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h00)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h04)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h08)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h0c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h10)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h14)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h18)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h1c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h20)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h24)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h28)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h2c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h30)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h34)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h38)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h3c)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h40)), (!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h44))] |
2 |
`REGS_IDLE |
`REGS_HWRITE |
[(!(~ pi_host_reset) && (device_selected) && (pi_config_mcmd == 2’b01) && (rw_addr == 7’h48))] |
3 |
`REGS_IDLE |
`REGS_READ |
[(!(~ pi_host_reset) && (device_selected) && !(pi_config_mcmd == 2’b01) && (pi_config_mcmd == 2’b10))] |
4 |
`REGS_WRITE |
`REGS_IDLE |
[!(~ pi_host_reset)] |
5 |
`REGS_HWRITE |
`REGS_WRITE |
[(!(~ pi_host_reset) && (hash_cnt == 1))] |
6 |
`REGS_READ |
`REGS_IDLE |
[!(~ pi_host_reset)] |
7 |
default |
`REGS_IDLE |
[!(~ pi_host_reset)] |
Instances
- ip_emac_topip_emac_top
regs_bank
general interface host domain reset