Module ip_mac_rx_sync_g
Name |
Direction |
Type |
Description |
---|---|---|---|
pi_rx_reset |
input |
wire logic |
|
pi_rx_f_clock |
input |
wire logic |
Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_host_idone |
output |
var reg |
Reset done Receive initialisation done (host clock domain) |
pi_host_reset |
input |
wire logic |
Host clock and reset Global Hardware/Software reset (host clock domain, active low) |
pi_host_f_clock |
input |
wire logic |
Host clock (from Clock Manager) |
pi_rx_stop |
input |
wire logic |
Inputs -> Synchronized outputs Receive stop command acknowledge (receive clock domain) |
po_host_stop |
output |
var reg |
Receive stop command acknowledge (synchronized to host clock domain) |
pi_host_stop |
input |
wire logic |
Receive stop command (host clock domain) |
po_rx_stop |
output |
var reg |
Receive stop command (synchronized to receive clock domain) |
pi_tx_xmit_nfc |
input |
wire logic |
Transmit FSM data frame transmit enable (transmit clock domain) |
po_rx_xmit_nfc |
output |
var reg |
NOTE: This signal is not asserted during flow control frame transmission Transmit FSM data frame transmit enable (synchronized to receive clock domain) |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
rx_sync
Receive clock and reset Global Hardware/Software reset (receive clock domain, active low)