Module ip_mac_hostif_top

ip_mac_hostif_top u_ip_mac_hostif_top ( .pi_reset(pi_reset), .pi_clock_f(pi_clock_f), .pi_rx_clock(pi_rx_clock), .pi_rxds_clock(pi_rxds_clock), .pi_tx_clock(pi_tx_clock), .pi_txds_clock(pi_txds_clock), .pi_tx1_clock(pi_tx1_clock), .po_rx_clock_en(po_rx_clock_en), .po_rxds_clock_en(po_rxds_clock_en), .po_tx_clock_en(po_tx_clock_en), .po_txds_clock_en(po_txds_clock_en), .po_tx1_clock_en(po_tx1_clock_en), .po_host_mcmd(po_host_mcmd), .po_host_maddr(po_host_maddr), .po_host_mdata(po_host_mdata), .po_host_mlast(po_host_mlast), .pi_host_sdata(pi_host_sdata), .pi_host_sdva(pi_host_sdva), .po_rx_enable_rd(po_rx_enable_rd), .pi_rx_empty(pi_rx_empty), .pi_rx_last_rd(pi_rx_last_rd), .pi_rx_data(pi_rx_data), .pi_rx_sof(pi_rx_sof), .pi_rx_eof(pi_rx_eof), .po_tx_enable_wr(po_tx_enable_wr), .pi_tx_full(pi_tx_full), .pi_tx_last_wr(pi_tx_last_wr), .po_tx_data(po_tx_data), .po_tx_be(po_tx_be), .po_tx_sof(po_tx_sof), .po_tx_eof(po_tx_eof), .po_tx_err(po_tx_err), .po_tx_put_crc(po_tx_put_crc), .po_tx_put_padding(po_tx_put_padding), .po_tx_upd_read(po_tx_upd_read), .pi_tx_upd_empty(pi_tx_upd_empty), .pi_tx_upd_last(pi_tx_upd_last), .pi_tx_upd_data(pi_tx_upd_data), .pi_regs_csr0_tap(pi_regs_csr0_tap), .pi_regs_csr0_ape(pi_regs_csr0_ape), .pi_regs_csr0_bar(pi_regs_csr0_bar), .pi_regs_csr14_swr(pi_regs_csr14_swr), .pi_regs_csr1_tpd(pi_regs_csr1_tpd), .pi_regs_csr2_rpd(pi_regs_csr2_rpd), .pi_regs_csr3_stl(pi_regs_csr3_stl), .pi_regs_csr4_srl(pi_regs_csr4_srl), .po_regs_csr5_rwt(po_regs_csr5_rwt), .po_regs_csr5_unf(po_regs_csr5_unf), .po_regs_csr5_ovf(po_regs_csr5_ovf), .po_regs_csr5_ru(po_regs_csr5_ru), .po_regs_csr5_tu(po_regs_csr5_tu), .po_regs_csr5_ri(po_regs_csr5_ri), .po_regs_csr5_ti(po_regs_csr5_ti), .po_regs_csr5_tjt(po_regs_csr5_tjt), .pi_regs_csr14_st(pi_regs_csr14_st), .pi_regs_csr14_sr(pi_regs_csr14_sr), .pi_global_cfda_slm(pi_global_cfda_slm), .pi_global_cfda_szm(pi_global_cfda_szm), .pi_config_burst_size(pi_config_burst_size), .pi_config_ds_offset(pi_config_ds_offset) );

Block Diagram of ip_mac_hostif_top

Ports

Name	Direction	Type	Description
pi_reset	input	wire logic	global asynchronous reset
pi_clock_f	input	wire logic	host clock
pi_rx_clock	input	wire logic
pi_rxds_clock	input	wire logic
pi_tx_clock	input	wire logic
pi_txds_clock	input	wire logic
pi_tx1_clock	input	wire logic
po_rx_clock_en	output	wire logic	clock enable for gated clocks
po_rxds_clock_en	output	wire logic
po_tx_clock_en	output	wire logic
po_txds_clock_en	output	wire logic
po_tx1_clock_en	output	wire logic
po_host_mcmd	output	wire logic[1:0]	command
po_host_maddr	output	wire logic[31:0]	address
po_host_mdata	output	wire logic[31:0]	data to write
po_host_mlast	output	wire logic	last word
pi_host_sdata	input	wire logic[31:0]	data to read
pi_host_sdva	input	wire logic	data valid
po_rx_enable_rd	output	wire logic	rx fifo read command
pi_rx_empty	input	wire logic	rx fifo full
pi_rx_last_rd	input	wire logic	rx fifo almost full
pi_rx_data	input	wire logic[31:0]	rx fifo data
pi_rx_sof	input	wire logic	rx fifo eof
pi_rx_eof	input	wire logic	rx fifo eof
po_tx_enable_wr	output	wire logic	rx fifo read command
pi_tx_full	input	wire logic	rx fifo full
pi_tx_last_wr	input	wire logic	rx fifo almost full
po_tx_data	output	wire logic[31:0]	rx fifo data
po_tx_be	output	wire logic[1:0]	tx fifo data byte enable
po_tx_sof	output	wire logic	tx fifo start of frame
po_tx_eof	output	wire logic	tx fifo end of frame
po_tx_err	output	wire logic	tx fifo error
po_tx_put_crc	output	wire logic	put crc indication (valid only when sof=1)
po_tx_put_padding	output	wire logic	put padding indication (valid only when sof=1)
po_tx_upd_read	output	wire logic
pi_tx_upd_empty	input	wire logic
pi_tx_upd_last	input	wire logic
pi_tx_upd_data	input	wire logic[9:0]
pi_regs_csr0_tap	input	wire logic[15:0]	tx automatic polling period CSR0[31:16]
pi_regs_csr0_ape	input	wire logic	tx auto polling enable CSR[15]
pi_regs_csr0_bar	input	wire logic	bus arbitration
pi_regs_csr14_swr	input	wire logic	software reset
pi_regs_csr1_tpd	input	wire logic	transmit poll demand
pi_regs_csr2_rpd	input	wire logic	receive poll demand
pi_regs_csr3_stl	input	wire logic[29:0]	transmit descriptor base address
pi_regs_csr4_srl	input	wire logic[29:0]	receive descriptor base address
po_regs_csr5_rwt	output	wire logic	receive watchdog timeout
po_regs_csr5_unf	output	wire logic	transmit underflow
po_regs_csr5_ovf	output	wire logic	receive overflow
po_regs_csr5_ru	output	wire logic	receive buffer unavailable
po_regs_csr5_tu	output	wire logic	transmit buffer unavailable
po_regs_csr5_ri	output	wire logic	receive interupt
po_regs_csr5_ti	output	wire logic	transmit interupt
po_regs_csr5_tjt	output	wire logic	signals Transmit jabber timeout error to the CSR5 register; this will signal to the HOST to perform a software reset to the EMAC
pi_regs_csr14_st	input	wire logic	start/stop transmit
pi_regs_csr14_sr	input	wire logic	start / stop receive
pi_global_cfda_slm	input	wire logic	sleep mode enable
pi_global_cfda_szm	input	wire logic	snooze mode enable
pi_config_burst_size	input	wire logic[5:0]	limit for the rx,tx burst transfers
pi_config_ds_offset	input	wire logic[4:0]	offset to increment the address if a descriptor

Instances

• ip_emac_topip_emac_top

  • host_if

Submodules

• ip_mac_hostif_top

  • hostif_arb : ip_mac_hostif_arb

  • hostif_rx : ip_mac_hostif_rx

  • hostif_rxds : ip_mac_hostif_rxds

  • hostif_tx : ip_mac_hostif_tx

  • hostif_txds : ip_mac_hostif_txds

Reset

Schematic Diagram of ip_mac_hostif_top

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