Module ip_emac_top
Name |
Direction |
Type |
Description |
---|---|---|---|
pi_emac_reset |
input |
wire logic |
|
pi_emac_ref_clock |
input |
wire logic |
GMII 125 MHz reference clock |
pi_emac_tx_clock |
input |
wire logic |
Transmit GMII/MII interface Transmit MII 25/2.5 MHz clock (from PHY) |
po_emac_gtx_clock |
output |
wire logic |
Transmit GMII 125 MHz clock (to PHY) |
po_emac_tx_en |
output |
wire logic |
Transmit MII/GMII enable indication (to PHY) |
po_emac_tx_err |
output |
wire logic |
Transmit MII/GMII error indication (to PHY) |
po_emac_tx_data |
output |
wire logic[7:0] |
Transmit MII/GMII data (MII data is po_emac_tx_data[3:0]) (to PHY) |
pi_emac_tx_col |
input |
wire logic |
Collision indication (from PHY) |
pi_emac_tx_crs |
input |
wire logic |
Carrier Sense indication (from PHY) |
pi_emac_rx_clock |
input |
wire logic |
Receive GMII/MII interface Receive GMII/MII 125/25/2.5 MHz clock (from PHY) |
pi_emac_rx_dv |
input |
wire logic |
Receive MII/GMII data valid indication (from PHY) |
pi_emac_rx_err |
input |
wire logic |
Receive MII/GMII error indication (from PHY) |
pi_emac_rx_data |
input |
wire logic[7:0] |
Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY) |
pi_emac_host_clock |
input |
wire logic |
HOST interface (common) |
pi_emac_base_address |
input |
wire logic[23:0] |
host data interface |
po_emac_host_mcmd |
output |
wire logic[1:0] |
|
po_emac_host_maddr |
output |
wire logic[31:0] |
|
po_emac_host_mdata |
output |
wire logic[31:0] |
|
po_emac_host_mlast |
output |
wire logic |
|
pi_emac_host_sdata |
input |
wire logic[31:0] |
|
pi_emac_host_sdva |
input |
wire logic |
|
pi_emac_host_serr |
input |
wire logic |
|
pi_emac_config_mcmd |
input |
wire logic[1:0] |
host config interface |
pi_emac_config_maddr |
input |
wire logic[31:0] |
|
pi_emac_config_mdata |
input |
wire logic[31:0] |
|
po_emac_config_sdata |
output |
wire logic[31:0] |
pi_emac_config_mlast , |
po_emac_config_sdva |
output |
wire logic |
|
po_emac_config_serr |
output |
wire logic |
|
po_host_int |
output |
wire logic |
general interrupt to host |
pi_emac_mdio_clock |
input |
wire logic |
MDIO interface |
po_emac_mdio_clock |
output |
wire logic |
|
pi_emac_master_mdio |
input |
wire logic |
|
po_emac_master_mdio |
output |
wire logic |
|
po_emac_master_oni |
output |
wire logic |
|
pi_mac_test_en |
input |
wire logic |
Test and Scan interface signals |
pi_mac_scan_en |
input |
wire logic |
|
pi_mac_scan_in |
input |
wire logic |
|
po_mac_scan_out |
output |
wire logic |
|
pi_bistmode_en |
input |
wire logic |
Submodules
- ip_emac_top
host_clk_mng : ip_host_clk_mng_g
host_if : ip_mac_hostif_top
mac_top : ip_mac_top_g #(.TX_MEM_ADDR(10), .RX_MEM_ADDR(10))
regs_bank : ip_mac_regs_bank
Global Hardware reset (active low)