Host Master Interface Single Read/Write Timing

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This figure presents the host interface timing when single commands are used. The ip_emac_host_mlast asserted high indicates that single command is issued. The ip_emac_host_mcmd transition to IDLE is determined by the assertion of ip_emac_host_sdva or ip_emac_host_serr signal. After the slave response for the current command the next command is loaded by the ip_emac_host_mcmd if available, else the IDLE state is loaded.

  1. The EMAC issues a single READ command

  2. The slave responds by asserting ip_emac_host_sdva and ip_emac_host_sdata

  3. The EMAC issues a single WRITE command

  4. The slave accepts the WRITE command by asserting ip_emac_host_sdva

  5. The EMAC issues a single READ command

  6. The slave responds by asserting ip_emac_host_serr (the transfer cannot be complete by the slave)

  7. The EMAC issues a single WRITE command

  8. The slave responds by asserting ip_emac_host_serr (the transfer cannot be complete by the slave)