Module ip_sync_cell

ip_sync_cell u_ip_sync_cell ( .pi_reset_wr(pi_reset_wr), .pi_reset_rd(pi_reset_rd), .pi_clock_wr(pi_clock_wr), .pi_clock_rd(pi_clock_rd), .po_enable_wr(po_enable_wr), .po_enable_rd(po_enable_rd), .pi_ready_wr(pi_ready_wr), .pi_ready_rd(pi_ready_rd) );

Block Diagram of ip_sync_cell

Overview

The synchronization cell is responsible for the write/read enable signals synchronization. The write enable signal indicates that a new write clock domain data can be synchronized to the read clock domain. The read enable signal indicates that the external data can be safely read on the read clock domain.

Ports

Name	Direction	Type	Description
pi_reset_wr	input	wire logic	reset write clock domain (synchronous)
pi_reset_rd	input	wire logic	reset read clock domain (synchronous)
pi_clock_wr	input	wire logic	write clock
pi_clock_rd	input	wire logic	read clock
po_enable_wr	output	wire logic	write enable (combinatorial output)
po_enable_rd	output	wire logic	read enable (combinatorial output)
pi_ready_wr	input	wire logic	write ready (data available for write)
pi_ready_rd	input	wire logic	read ready (data available for read)

Instances

• ip_emac_topip_emac_top

  • mac_topip_mac_top_g

    • mac_rx_topip_mac_rx_top_g

      • rx_asyncip_async_fifo_g

        • cell_0

        • cell_1

        • cell_2

        • cell_3

        • cell_4

        • cell_5

        • cell_6

        • cell_7

    • mac_tx_topip_mac_tx_top_g

      • tx_data_asyncip_async_fifo_g

        • cell_0

        • cell_1

        • cell_2

        • cell_3

        • cell_4

        • cell_5

        • cell_6

        • cell_7

      • tx_stat_asyncip_async_fifo_g

        • cell_0

        • cell_1

        • cell_2

        • cell_3

        • cell_4

        • cell_5

        • cell_6

        • cell_7

Submodules

• ip_sync_cell

  • metastable_toggle_rd : dff_metastable #(.DFF_WIDTH(1))

  • metastable_toggle_wr : dff_metastable #(.DFF_WIDTH(1))

Reset

Schematic Diagram of ip_sync_cell

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