Module ip_mac_tx_fifo_g

ip_mac_tx_fifo_g #( .MEM_ADDR(MEM_ADDR) ) u_ip_mac_tx_fifo_g ( .pi_reset(pi_reset), .pi_f_clock(pi_f_clock), .pi_empty_rd(pi_empty_rd), .pi_last_rd(pi_last_rd), .po_enable_rd(po_enable_rd), .pi_rd_addr(pi_rd_addr), .po_wr_addr(po_wr_addr), .po_wr_en(po_wr_en), .po_wr_ptr(po_wr_ptr), .pi_store_fwd(pi_store_fwd), .pi_threshold(pi_threshold), .pi_end_of_pkt(pi_end_of_pkt) );

Block Diagram of ip_mac_tx_fifo_g

Overview

The EMAC Transmit FIFO Control module is responsible to generate all the control signals necessary to transfer the data form the EMAC Asynchronous FIFO module to the EMAC Transmit Memory module. The EMAC Transmit FIFO Control module provides the memory write pointer and the write address, used by the EMAC Transmit module in order to calculate if the memory is ready (actual frame transmission begins after the internal transmit memory had reached either a programmable threshold or after a full frame is contained in the memory). The write address is updated (takes the write pointer value) whenever the memory contains enough data for transmit. The pointer update is made when the number of words of the frame exceeds a programmed threshold value or the entire frame is in the memory.

Parameters

Name	Default value	Description
MEM_ADDR	6	Transmit memory address width (9 -> 512 locations, 10->1024)

Ports

Name	Direction	Type	Description
pi_reset	input	wire logic	Global Hardware/Software reset (active low)
pi_f_clock	input	wire logic	Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, free clock)
pi_empty_rd	input	wire logic	Signals from/to Asynchronous FIFO Asynchronous FIFO empty (no read can be performed)
pi_last_rd	input	wire logic	Asynchronous FIFO last valid location
po_enable_rd	output	var reg	Asynchronous FIFO read enable
pi_rd_addr	input	wire logic[MEM_ADDR:0]	Signals from MAC State Machine Used by TX FIFO to compute the memory state (full/empty/ready)
po_wr_addr	output	var reg[MEM_ADDR:0]	Used by EMAC Transmit State to compute the memory state (full/empty/ready)
po_wr_en	output	wire logic	Signals to memory (synchronous FIFO block) Write memory enable
po_wr_ptr	output	var reg[MEM_ADDR:0]	Write pointer used by the memory to store data
pi_store_fwd	input	wire logic	Configuration Interface Store and forward / Cut trught
pi_threshold	input	wire logic[MEM_ADDR-1:0]	Cut trught threshold
pi_end_of_pkt	input	wire logic	The end of packet/frame is stored into memory

Always Blocks

always @ ( posedge pi_f_clock or negedge pi_reset )

Assign Read async FIFO/Write sync FIFO enable

Reset

FSM Transitions for po_enable_rd

#	Current State	Next State	Condition
1	1’b1	1’b0	[(!(~ pi_reset) && !(po_wr_ptr[MEM_ADDR] != pi_rd_addr[MEM_ADDR] && po_wr_ptr[MEM_ADDR - 1 : 0] == pi_rd_addr[MEM_ADDR - 1 : 0]) && !(wr_inc[MEM_ADDR] != pi_rd_addr[MEM_ADDR] && wr_inc[MEM_ADDR - 1 : 0] == pi_rd_addr[MEM_ADDR - 1 : 0] && po_wr_en == 1’b1) && !(pi_empty_rd == 1’b1))]

Instances

• ip_emac_topip_emac_top

  • mac_topip_mac_top_g

    • mac_tx_topip_mac_tx_top_g

      • tx_fifo : ip_mac_tx_fifo_g#(.MEM_ADDR(10))

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