Module ip_mac_hostif_arb

pi_resetlogicpi_clocklogicpi_tx_frame_transmitlogicpi_regs_csr0_barlogicpi_rx_reqlogicpi_tx_reqlogicpi_rx_ds_reqlogicpi_tx_ds_reqlogicpi_tx_upd_reqlogicpi_rx_mcmd[1:0]logicpi_rx_maddr[31:0]logicpi_rx_mdata[31:0]logicpi_rx_mlastlogicpi_tx_mcmd[1:0]logicpi_tx_maddr[31:0]logicpi_tx_mlastlogicpi_rx_ds_mcmd[1:0]logicpi_rx_ds_maddr[31:0]logicpi_rx_ds_mlastlogicpi_tx_ds_mcmd[1:0]logicpi_tx_ds_maddr[31:0]logicpi_tx_ds_mlastlogicpi_tx_upd_mcmd[1:0]logicpi_tx_upd_maddr[31:0]logicpi_tx_upd_mdata[31:0]logicpi_tx_upd_mlastlogicpo_host_mcmdreg[1:0]po_host_maddrreg[31:0]po_host_mdatareg[31:0]po_host_mlastregpo_rx_allowedregpo_rx_ds_allowedregpo_tx_allowedregpo_tx_ds_allowedregpo_tx_upd_allowedreg

Block Diagram of ip_mac_hostif_arb

Ports

Name

Direction

Type

Description

pi_reset

input

wire logic

Global interface global asynchronous pi_reset

pi_clock

input

wire logic

host pi_clock

pi_tx_frame_transmit

input

wire logic

from pi_mac_hostif_tx

pi_regs_csr0_bar

input

wire logic

from banks regs

pi_rx_req

input

wire logic

pi_tx_req

input

wire logic

pi_rx_ds_req

input

wire logic

pi_tx_ds_req

input

wire logic

pi_tx_upd_req

input

wire logic

pi_rx_mcmd

input

wire logic[1:0]

pi_rx_maddr

input

wire logic[31:0]

pi_rx_mdata

input

wire logic[31:0]

pi_rx_mlast

input

wire logic

pi_tx_mcmd

input

wire logic[1:0]

pi_tx_maddr

input

wire logic[31:0]

pi_tx_mlast

input

wire logic

pi_tx_mdata,

pi_rx_ds_mcmd

input

wire logic[1:0]

pi_rx_ds_maddr

input

wire logic[31:0]

pi_rx_ds_mlast

input

wire logic

pi_tx_ds_mcmd

input

wire logic[1:0]

pi_tx_ds_maddr

input

wire logic[31:0]

pi_tx_ds_mlast

input

wire logic

pi_tx_upd_mcmd

input

wire logic[1:0]

pi_tx_upd_maddr

input

wire logic[31:0]

pi_tx_upd_mdata

input

wire logic[31:0]

pi_tx_upd_mlast

input

wire logic

po_host_mcmd

output

var reg[1:0]

po_host_maddr

output

var reg[31:0]

po_host_mdata

output

var reg[31:0]

po_host_mlast

output

var reg

po_rx_allowed

output

var reg

po_rx_ds_allowed

output

var reg

po_tx_allowed

output

var reg

po_tx_ds_allowed

output

var reg

po_tx_upd_allowed

output

var reg

Always Blocks

always @ ( arb_state or po_rx_allowed or po_tx_allowed or po_rx_ds_allowed or po_tx_ds_allowed or po_tx_upd_allowed )

arbiter next state calculation

`ARB_RX `ARB_RX = 3'b010 `ARB_TX `ARB_TX = 3'b011 `ARB_RX_DS `ARB_RX_DS = 3'b100 `ARB_TX_DS `ARB_TX_DS = 3'b101 `ARB_TX_UPD `ARB_TX_UPD = 3'b110 `ARB_IDLE `ARB_IDLE = 3'b000 `ARB_S0 `ARB_S0 = 3'b001 DEFAULT default 1 [!(~ pi_reset)]
FSM Transitions for arb_state

#

Current State

Next State

Condition

1

`ARB_IDLE

`ARB_S0

[!(~ pi_reset)]

Instances