Module ip_mac_rx_top_g
Block Diagram of ip_mac_rx_top_g
Name |
Default value |
Description |
|---|---|---|
RX_MEM_ADDR |
6 |
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_rx_reset |
input |
wire logic |
Global Software/Hardware Reset (receive clock domain) |
pi_host_reset |
input |
wire logic |
Global Software/Hardware Reset (host clock domain) |
pi_host_hw_rst |
input |
wire logic |
Global Hardware Reset (host clock domain) |
pi_rx_f_clock |
input |
wire logic |
Receive clock Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_rx_g_clock |
input |
wire logic[2:0] |
Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_rx_en_clock |
output |
wire logic[2:0] |
Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_host_init_done |
output |
wire logic |
Initialisation done Receive initialisation done (host clock domain) |
pi_tx_gmii_val |
input |
wire logic |
Loopback GMII/MII Data Valid, Data Input Signals and Alignment Error Loopback MII/GMII data valid indication (from TX) |
pi_tx_gmii_err |
input |
wire logic |
Loopback MII/GMII error indication (from TX) |
pi_tx_gmii_data |
input |
wire logic[7:0] |
Loopback MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from TX) |
pi_tx_xmit_nfc |
input |
wire logic |
Transmit full duplex data frame transmit enable pending (non flow control frame is transmitted) Transmit FSM data frame transmit enable (transmit clock domain) |
pi_rx_gmii_sel |
input |
wire logic |
NOTE: This signal is not asserted during flow control frame transmission GMII/MII Data Valid, Data Input Signals and Alignment Error Receive GMII data select (demultiplex MII interface indication) |
pi_gmii_val |
input |
wire logic |
Note: po_rx_gmii_sel is balanced with the internal receive clock Receive MII/GMII data valid indication (from PHY) |
pi_gmii_data |
input |
wire logic[7:0] |
Receive MII/GMII error indication (from PHY) |
pi_gmii_err |
input |
wire logic |
Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from PHY) |
pi_rx_gigabit |
input |
wire logic |
Operating 1000 Mbps (Gigabit) mode |
pi_rx_half_duplex |
input |
wire logic |
Operating Half Duplex mode |
pi_rx_loopback |
input |
wire logic |
Loopback mode select |
pi_rx_fc_enable |
input |
wire logic |
Receive flow control enable (flow control decoding enable) |
po_rx_fc_tx_off |
output |
wire logic |
Received FC packet (Transmit stop command) |
po_rx_fc_xoff_tgl |
output |
wire logic |
(to TX EMAC) insert XOFF flow control information |
po_rx_fc_xon_tgl |
output |
wire logic |
(to TX EMAC) insert XON flow control information |
pi_host_hash_nfix |
input |
wire logic |
Hash filtering + 1 Address match / 16 Address match |
pi_host_little |
input |
wire logic |
Little endian (data path organisation) |
pi_rx_hash_nfix |
input |
wire logic |
Configuration Filtering Hash/Exact Hash filtering + 1 Address match / 16 Address match |
pi_rx_inverse |
input |
wire logic |
Inverse match filtering mode |
pi_rx_multicast |
input |
wire logic |
When asserted the imperfect filtering refers only for multicast addressees |
pi_rx_pass_multi |
input |
wire logic |
Pass all multicast addresses |
pi_rx_promisc |
input |
wire logic |
Promiscuos Mode (no DA filter) |
pi_rx_pass_all |
input |
wire logic |
pass all bad frames (including FC frames) |
pi_rx_high_thrs |
input |
wire logic[RX_MEM_ADDR:0] |
from configuration FC high threshold |
pi_rx_low_thrs |
input |
wire logic[RX_MEM_ADDR:0] |
from configuration FC low threshold |
pi_host_wakeup |
input |
wire logic |
From/To Receive DMA (setup frame) Wake-up internal clock used by the Setup Frame FSM, |
pi_host_wr_data |
input |
wire logic[31:0] |
should be asserted at least 2 clock cycles (HOST clock) before asserting the pi_host_wr_setup (write enable) and can be deasserted 2 clock cycles after Setup Frame completition Setup Frame data (HOST clock synchronous) |
pi_host_wr_setup |
input |
wire logic |
Setup Frame write enable (HOST clock synchronous) |
pi_host_f_clock |
input |
wire logic |
Receive data path HOST interface Free HOST interface clock signal |
pi_host_g_clock |
input |
wire logic |
Gated Free HOST interface clock signal |
po_host_en_clock |
output |
wire logic |
Enable Free HOST interface clock signal |
pi_host_enable_rd |
input |
wire logic |
Receive MAC data path, HOST enable command |
po_host_empty_rd |
output |
wire logic |
Receive MAC data path, HOST FIFO empty indication |
po_host_last_rd |
output |
wire logic |
Receive MAC data path, HOST FIFO last location indication |
po_host_data_rd |
output |
wire logic[31:0] |
Receive MAC data path, HOST data (transmit data) |
po_host_byte_rd |
output |
wire logic[1:0] |
Receive MAC data path, HOST byte enable (transmit data byte enable) |
po_host_start_rd |
output |
wire logic |
Receive MAC data path, HOST start of frame indication |
po_host_end_rd |
output |
wire logic |
Receive MAC data path, HOST start of frame indication |
po_host_error_rd |
output |
wire logic |
Receive MAC data path, HOST frame error indication (asserted when |
pi_host_stop_rcv |
input |
wire logic |
frame is bigger than 64 bytes and receive MAC cannot drop the frame or pass bad frames mode is selected by asserting pi_emac_pass_all) Receive Start/Stop Receive MAC, receive stopped indication (HOST clock synchronous) |
po_host_stop_rcv |
output |
wire logic |
Receive MAC, receive stop command (HOST clock synchronous) |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
mac_rx_top : ip_mac_rx_top_g#(.RX_MEM_ADDR(10))
Submodules
- ip_mac_rx_top_g#(.RX_MEM_ADDR(10))
cfg_hash : ip_mac_cfg_hash_g
fc_dec : ip_mac_fc_dec_g
rx_async : ip_async_fifo_g #(.MEM_WIDTH(37))
rx_data_dram : ip_mac_dram_002 #(.MEM_ADDR(10), .MEM_WIDTH(37))
rx_dram_hash_0 : ip_mac_dram_004 #(.MEM_ADDR(4), .MEM_WIDTH(32))
rx_dram_hash_1 : ip_mac_dram_003 #(.MEM_ADDR(4), .MEM_WIDTH(16))
rx_endian : ip_mac_big_endian
rx_fifo : ip_mac_rx_fifo_g #(.MEM_ADDR(10))
rx_gmii : ip_mac_rx_gmii_g
rx_hash : ip_mac_rx_hash_g
rx_state : ip_mac_rx_state_g #(.MEM_ADDR(10))
rx_sync : ip_mac_rx_sync_g
Schematic Diagram of ip_mac_rx_top_g
Receive memory address width (9 -> 512 locations, 10->1024)