Module dff_metastable
Name |
Default value |
Description |
---|---|---|
DFF_WIDTH |
1 |
Name |
Direction |
Type |
Description |
---|---|---|---|
reset |
input |
wire logic |
|
d |
input |
wire logic[DFF_WIDTH-1:0] |
|
clock |
input |
wire logic |
|
q |
output |
var reg[DFF_WIDTH-1:0] |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
- rx_asyncip_async_fifo_g
- cell_0ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_1ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_2ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_3ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_4ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_5ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_6ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_7ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- mac_tx_topip_mac_tx_top_g
- tx_data_asyncip_async_fifo_g
- cell_0ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_1ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_2ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_3ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_4ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_5ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_6ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_7ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- tx_stat_asyncip_async_fifo_g
- cell_0ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_1ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_2ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_3ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_4ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_5ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_6ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
- cell_7ip_sync_cell
metastable_toggle_rd : dff_metastable#(.DFF_WIDTH(1))
metastable_toggle_wr : dff_metastable#(.DFF_WIDTH(1))
Submodules
- dff_metastable#(.DFF_WIDTH(1))
dffrhqx1_0 : dffrhqx1