Module ip_mac_dram_004
Block Diagram of ip_mac_dram_004
Overview
Name |
Default value |
Description |
|---|---|---|
MEM_ADDR |
4 |
Address width (9 -> 512 locations, 10->1024) |
MEM_WIDTH |
32 |
Data width |
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_clock_wr |
input |
wire logic |
Input write clock (multiplexed with scan clock ouside this module) |
pi_clock_rd |
input |
wire logic |
Input read clock |
pi_addr_wr |
input |
wire logic[MEM_ADDR-1:0] |
Write address |
pi_addr_rd |
input |
wire logic[MEM_ADDR-1:0] |
Read address |
pi_wr_en |
input |
wire logic |
Write enable |
pi_data_wr |
input |
wire logic[MEM_WIDTH-1:0] |
Write data |
po_data_rd |
output |
wire logic[MEM_WIDTH-1:0] |
Read data |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
rx_dram_hash_0 : ip_mac_dram_004#(.MEM_ADDR(4), .MEM_WIDTH(32))
Submodules
- ip_mac_dram_004#(.MEM_ADDR(4), .MEM_WIDTH(32))
dram_001 : dram_001 #(.MEM_ADDR(4), .MEM_WIDTH(32))
Schematic Diagram of ip_mac_dram_004
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The internal DRAM memory modules have the property that when the read address selects a memory location, this location is write protected (locked for write operation). Since when FIFO is empty both read and write addresses points to the same address and the a write operation should be performed, the read memory address should point to an unused memory location in order to unlock the write operation. Moving the internal address to an unused location when write enable modifies the read operation timing since the read DRAM address does not point to the right read address. In order to avoid the timing read response delay a bypass register between input and output data is used. When FIFO is empty the output data reads the bypass register instead of DRAM memory output.
Note: No bypass is necessary for Hash table memory since the read is not performed in the same time memory is writed. Bypass data register and bypass select multiplexer is removed from this module