Module ip_mac_hostif_rx
Block Diagram of ip_mac_hostif_rx
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_reset |
input |
wire logic |
|
pi_g_clock |
input |
wire logic |
host gated clock |
pi_f_clock |
input |
wire logic |
host free clock |
po_en_clock |
output |
var reg |
enable clock condition |
po_rx_enable_rd |
output |
wire logic |
RX FIFO interface rx fifo read command |
pi_rx_empty |
input |
wire logic |
rx fifo full |
pi_rx_last_rd |
input |
wire logic |
rx fifo almost full |
pi_rx_data |
input |
wire logic[31:0] |
rx fifo data |
pi_rx_sof |
input |
wire logic |
rx fifo eof |
pi_rx_eof |
input |
wire logic |
rx fifo eof |
rx_ds_addr_valid |
input |
wire logic |
ip_mac_hostif_rxds from ip_mac_hostif_rxds (currently fetched descriptor address valid) |
rx_ds_next_addr |
input |
wire logic[31:0] |
from ip_mac_hostif_rxds (currently fetched descriptor address) |
rx_valid_ds_read |
output |
var reg |
|
po_rx_ds1 |
output |
wire logic[1:0] |
mapped to rx, rx_ds1[25:24] |
po_rx_ds3 |
output |
wire logic[31:0] |
|
rx_req |
output |
var reg |
arbiter |
rx_allowed |
input |
wire logic |
|
rx_mcmd |
output |
var reg[1:0] |
|
rx_maddr |
output |
var reg[31:0] |
|
rx_mdata |
output |
var reg[31:0] |
|
rx_mlast |
output |
var reg |
|
pi_host_sdva |
input |
wire logic |
host interface |
pi_host_sdata |
input |
wire logic[31:0] |
|
pi_regs_csr14_sr |
input |
wire logic |
ip_mac_regs_bank (config) |
pi_config_burst_size |
input |
wire logic[5:0] |
limit for the rx,tx burst transfers |
po_regs_csr5_ri |
output |
var reg |
|
po_regs_csr5_ovf |
output |
var reg |
|
po_regs_csr5_rwt |
output |
var reg |
Always Blocks
- always @ ( posedge pi_f_clock or negedge pi_reset )
Gated Clock Enable
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`RX_IDLE |
`RX_READ_DS |
[(!(~ pi_reset) && !(! rx_ds_addr_valid) && !(rx_ds_addr_valid && ! rx_req) && (rx_allowed))] |
2 |
`RX_READ_DS |
`RX_WRITE_PAUSE |
[(!(~ pi_reset) && (pi_host_sdva) && !(rx_burst_cnt == 0) && !(rx_burst_cnt == 1) && (rx_burst_cnt == 2))] |
3 |
`RX_WRITE_PAUSE |
`RX_IDLE |
[(!(~ pi_reset) && (! rx_ds_valid))] |
4 |
`RX_WRITE_PAUSE |
`RX_WRITE |
[(!(~ pi_reset) && !(! rx_ds_valid) && !(! pi_rx_empty && ! pi_rx_last_rd && ! rx_req) && (rx_allowed))] |
5 |
`RX_WRITE |
`RX_STAT |
[(!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && (rx_frame_complete))] |
6 |
`RX_WRITE |
`RX_WRITE_DS |
[(!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && (rx_buff_complete) && !(! rx_cur_buff && ! rx_ds1[24] && rx_ds1[21 : 11] != 0))] |
7 |
`RX_WRITE |
`RX_WRITE_PAUSE |
[(!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && !(rx_buff_complete) && (rx_burst_complete)), (!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && !(rx_buff_complete) && !(rx_burst_complete)), (!(~ pi_reset) && !(rx_first_word_in_burst) && !(! pi_host_sdva) && (rx_mlast) && !(rx_frame_complete) && (rx_buff_complete) && (! rx_cur_buff && ! rx_ds1[24] && rx_ds1[21 : 11] != 0))] |
8 |
`RX_STAT |
`RX_WRITE_DS |
[(!(~ pi_reset) && (! pi_rx_empty))] |
9 |
`RX_WRITE_DS |
`RX_IDLE |
[(!(~ pi_reset) && (rx_allowed && pi_host_sdva))] |
Instances
- ip_emac_topip_emac_top
- host_ifip_mac_hostif_top
hostif_rx
Global interface global asynchronous pi_reset