Module ip_mac_rx_fifo_g

MEM_ADDRpi_resetlogicpi_f_clocklogicpi_full_wrlogicpi_last_wrlogicpi_wr_ptr[MEM_ADDR:0]logicpi_wr_addr[MEM_ADDR:0]logicpi_wr_soflogicpi_wr_enlogicpi_high_thrs[MEM_ADDR:0]logicpi_low_thrs[MEM_ADDR:0]logicpo_enable_wrregpo_rd_addrreg[MEM_ADDR:0]po_fc_xoff_tglregpo_fc_xon_tglreg

Block Diagram of ip_mac_rx_fifo_g

Overview

The EMAC Receive FIFO Control module is responsible to generate all the control signals necessary to transfer the data form the EMAC Receive Memory module to the EMAC Asynchronous FIFO module. The EMAC Receive FIFO Control module provides the memory write memory pointer and the write address, used by the EMAC Receive module in order to calculate if the memory is ready (actual frame transmission begins after the internal Receive memory had reached either a programmable threshold or after a full frame is contained in the memory). The write address is updated (takes the write pointer value) whenever the memory contains enough data for Receive. The pointer update is made when the number of words of the frame exceeds a programmed threshold value or the entire frame is in the memory.

Parameters

Name

Default value

Description

MEM_ADDR

6

Transmit memory address width (9 -> 512 locations, 10->1024)
Ports

Name

Direction

Type

Description

pi_reset

input

wire logic

Global Hardware/Software reset (active low)

pi_f_clock

input

wire logic

Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager)

pi_full_wr

input

wire logic

Signals from/to Asynchronous FIFO Asynchronous FIFO full (no write can be performed)

pi_last_wr

input

wire logic

Asynchronous FIFO last valid location

po_enable_wr

output

var reg

Asynchronous FIFO write enable

pi_wr_ptr

input

wire logic[MEM_ADDR:0]

Signals from MAC State Machine
Used by RX FIFO to compute the memory state (full/empty/ready)

pi_wr_addr

input

wire logic[MEM_ADDR:0]

Write address (memory write address)

po_rd_addr

output

var reg[MEM_ADDR:0]

Used by EMAC Receive State to see the momory state (full/empty/ready)

pi_wr_sof

input

wire logic

Memory SOF and write enable (use for fc toggle function) Start of frame indication (resend a new FC packet since

pi_wr_en

input

wire logic

a new frame was received during pause period, a previously FC was send) FIFO write enable (valid start of frame)

pi_high_thrs

input

wire logic[MEM_ADDR:0]

Flow control From configuration FC high threshold

pi_low_thrs

input

wire logic[MEM_ADDR:0]

From configuration FC low threshold

po_fc_xoff_tgl

output

var reg

(to TX EMAC) insert XOFF flow control information

po_fc_xon_tgl

output

var reg

(to TX EMAC) insert XON flow control information

Always Blocks

always @ ( posedge pi_f_clock or negedge pi_reset )

Low/High Threshold Assignment

1'b1 1'b1 1'b0 1'b0 1 [(!(~ pi_reset) && !(pi_high_thrs < fifo_level && pi_wr_en == 1'b1 && pi_wr_sof == 1'b1))]
FSM Transitions for high_low_en

#

Current State

Next State

Condition

1

1’b1

1’b0

[(!(~ pi_reset) && !(pi_high_thrs < fifo_level && pi_wr_en == 1’b1 && pi_wr_sof == 1’b1))]
always @ ( posedge pi_f_clock or negedge pi_reset )

Write Enable & Address/Pointer Update Process

1'b0 1'b0 1'b1 1'b1 1 [(!(~ pi_reset) && !(valid_data == 1'b0) && !(pi_full_wr == 1'b1))]
FSM Transitions for po_enable_wr

#

Current State

Next State

Condition

1

1’b1

1’b0

[(!(~ pi_reset) && !(valid_data == 1’b0) && !(pi_full_wr == 1’b1))]

Instances