Module ip_mac_tx_fsm_g
Block Diagram of ip_mac_tx_fsm_g
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_reset |
input |
wire logic |
|
pi_g_clock |
input |
wire logic |
Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, gated clock) |
pi_f_clock |
input |
wire logic |
Transmit GMII/MII 125/25/2.5 MHz clock (from Clock Manager, free clock) |
po_en_clock |
output |
var reg |
Transmit GMII/MII 125/25/2.5 MHz clock gated clock enable |
pi_sop |
input |
wire logic |
Signals comming in from the data FIFO related to data transfer Start of data frame indication |
pi_eop |
input |
wire logic |
End of data frame indication |
pi_pad |
input |
wire logic |
Pad append command, valid only when end of frame (When padding enable |
pi_crc |
input |
wire logic |
and frame has less than 64 bytes the CRC is appended regardless of the CRC append setting CRC append command, valid only when end of frame |
pi_valid |
input |
wire logic |
Valid data |
pi_fc_req |
input |
wire logic |
Request & Acknowledge Flow control frame transmit request |
pi_data_req |
input |
wire logic |
Data frame transmit request |
po_fc_ack |
output |
var reg |
Flow control frame transmit acknowledge |
po_data_ack |
output |
var reg |
Data frame transmit acknowledge |
po_read |
output |
var reg |
Read & Retransmit & Drop current frame Read next data |
po_remove |
output |
var reg |
Remove current frame (drop frame) |
po_reload |
output |
var reg |
Reload current frame (retransmit) |
po_mac_state |
output |
var reg[3:0] |
Transmit FSM state Transmit FSM state current |
po_update |
output |
var reg |
Collision window Collision window (update read pointer) |
po_en_high |
output |
var reg |
Enable increment counter |
pi_half_duplex |
input |
wire logic |
Half duplex flow control enable Half duplex operating mode |
pi_hd_fc_en |
input |
wire logic |
Half-Duplex Flow Control enable |
pi_stop_xmit |
input |
wire logic |
Transmit start/stop Transmit EMAC stop command |
po_stop_xmit |
output |
var reg |
Transmit EMAC stopped |
po_bk_reset |
output |
var reg |
Control Signals Related to the Backoff Block Backoff counter reset command |
po_bk_start |
output |
var reg |
Backoff algorithm start command |
pi_bk_done |
input |
wire logic |
Backoff done indication |
pi_deferring |
input |
wire logic |
Control Signal from the deferral counter Defer current transmition (when asserted high) |
pi_deferred |
input |
wire logic |
Deferred frame statistic information (asserted for one cycle) |
pi_gigabit |
input |
wire logic |
Operating 1000 Mbps (Gigabit) mode |
pi_burst_lim |
input |
wire logic[15:0] |
Burst limit (valid only when operating mode is 1000 Mbps) |
pi_burst_en |
input |
wire logic |
Burst enable (valid only when operating mode is 1000 Mbps) |
po_burst_en |
output |
var reg |
Burst enable (valid only when operating mode is 1000 Mbps) |
pi_gmii_en |
input |
wire logic |
GMII Interface Transmit MII/GMII enable indication (to PHY) |
pi_gmii_col |
input |
wire logic |
Collision indication (from PHY) |
pi_gmii_crs |
input |
wire logic |
Carrier Sense indication (from PHY) |
po_xmit_nfc |
output |
wire logic |
(compensate the tx_gmii latency, connected to po_gmii_en on MII/GMII module) Transmit full duplex data frame transmit enable pending (non flow control frame is transmitted) Transmit FSM data frame transmit enable |
pi_stat_full |
input |
wire logic |
NOTE: This signal is not asserted during flow control frame transmission Statistic related signals Statistic FIFO full |
po_stat_data |
output |
wire logic[9:0] |
Statistic FIFO data |
po_stat_load |
output |
var reg |
Statistic FIFO write enable signal |
Always Blocks
- always @ ( posedge pi_g_clock or negedge pi_reset )
MAC State Decoder
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
1’b1 |
1’b0 |
[(!(~ pi_reset) && (po_mac_state == 4’h1)), (!(~ pi_reset) && (po_mac_state == 4’h1))] |
- always @ ( posedge pi_f_clock or negedge pi_reset )
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`TX_IDLE |
`TX_ERROR |
[(!(~ pi_reset) && (gmii_col == 1’b1 && po_burst_en == 1’b1))] |
2 |
`TX_IDLE |
`TX_STOP |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && (stop_xmit == 1’b1))] |
3 |
`TX_IDLE |
`TX_DEFER |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && !(stop_xmit == 1’b1) && (pi_fc_req == 1’b1)), (!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && !(stop_xmit == 1’b1) && !(pi_fc_req == 1’b1) && (pi_data_req == 1’b1))] |
4 |
`TX_IDLE |
`TX_PREAMBLE |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && !(stop_xmit == 1’b1) && !(pi_fc_req == 1’b1) && !(pi_data_req == 1’b1) && (gmii_crs == 1’b1 && gmii_crs_del == 1’b0 && pi_hd_fc_en == 1’b1))] |
5 |
`TX_ERROR |
`TX_BACKOFF |
[(!(~ pi_reset) && ({counter[1 : 0], po_en_high} == {1’b1, ~ pi_gigabit, pi_gigabit}))] |
6 |
`TX_STOP |
`TX_IDLE |
[(!(~ pi_reset) && (stop_xmit == 1’b0))] |
7 |
`TX_DEFER |
`TX_ERROR |
[(!(~ pi_reset) && (gmii_col == 1’b1 && po_burst_en == 1’b1))] |
8 |
`TX_DEFER |
`TX_PREAMBLE |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && (pi_deferring == 1’b0 && pi_sop == 1’b1)), (!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && !(pi_deferring == 1’b0 && pi_sop == 1’b1) && !(pi_deferring == 1’b0 && force_col == 1’b1) && (pi_deferring == 1’b0))] |
9 |
`TX_DEFER |
`TX_IDLE |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && po_burst_en == 1’b1) && !(pi_deferring == 1’b0 && pi_sop == 1’b1) && (pi_deferring == 1’b0 && force_col == 1’b1))] |
10 |
`TX_PREAMBLE |
`TX_ERROR |
[(!(~ pi_reset) && (gmii_col == 1’b1 && pi_gmii_en == 1’b0))] |
11 |
`TX_PREAMBLE |
`TX_JAM |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && pi_gmii_en == 1’b0) && (gmii_col == 1’b1))] |
12 |
`TX_PREAMBLE |
`TX_SFD |
[(!(~ pi_reset) && !(gmii_col == 1’b1 && pi_gmii_en == 1’b0) && !(gmii_col == 1’b1) && ({counter[2 : 1], po_en_high} == {2’d3, 1’b1}))] |
13 |
`TX_BACKOFF |
`TX_IDLE |
[(!(~ pi_reset) && (col_counter[4] == 1’b1 || window_out == 1’b1)), (!(~ pi_reset) && !(col_counter[4] == 1’b1 || window_out == 1’b1) && (pi_bk_done == 1’b1 && po_bk_start == 1’b0))] |
14 |
`TX_JAM |
`TX_BACKOFF |
[(!(~ pi_reset) && ({counter[1 : 0], po_en_high} == {1’b1, ~ pi_gigabit | force_col, pi_gigabit | force_col}))] |
15 |
`TX_SFD |
`TX_JAM |
[(!(~ pi_reset) && (po_en_high == 1’b1 && force_col == 1’b1 || gmii_col == 1’b1))] |
16 |
`TX_SFD |
`TX_DATA |
[(!(~ pi_reset) && !(po_en_high == 1’b1 && force_col == 1’b1 || gmii_col == 1’b1) && (po_en_high == 1’b1))] |
17 |
`TX_DATA |
`TX_JAM |
[(!(~ pi_reset) && (gmii_col == 1’b1))] |
18 |
`TX_DATA |
`TX_IDLE |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && (counter[14] == 1’b1 && counter[0] == 1’b1 && po_en_high == 1’b1)), (!(~ pi_reset) && !(gmii_col == 1’b1) && !(counter[14] == 1’b1 && counter[0] == 1’b1 && po_en_high == 1’b1) && (pi_valid == 1’b0 && po_en_high == 1’b1))] |
19 |
`TX_DATA |
`TX_PAD |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && !(counter[14] == 1’b1 && counter[0] == 1’b1 && po_en_high == 1’b1) && !(pi_valid == 1’b0 && po_en_high == 1’b1) && (int_eop == 1’b1 && count_60 == 1’b0 && pi_pad == 1’b1 && po_en_high == 1’b1))] |
20 |
`TX_DATA |
`TX_CRC |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && !(counter[14] == 1’b1 && counter[0] == 1’b1 && po_en_high == 1’b1) && !(pi_valid == 1’b0 && po_en_high == 1’b1) && !(int_eop == 1’b1 && count_60 == 1’b0 && pi_pad == 1’b1 && po_en_high == 1’b1) && (int_eop == 1’b1 && pi_crc == 1’b1 && po_en_high == 1’b1))] |
21 |
`TX_DATA |
`TX_EXTEND |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && !(counter[14] == 1’b1 && counter[0] == 1’b1 && po_en_high == 1’b1) && !(pi_valid == 1’b0 && po_en_high == 1’b1) && !(int_eop == 1’b1 && count_60 == 1’b0 && pi_pad == 1’b1 && po_en_high == 1’b1) && !(int_eop == 1’b1 && pi_crc == 1’b1 && po_en_high == 1’b1) && (int_eop == 1’b1 && count_512 == 1’b0 && burst_begin == 1’b1 && pi_half_duplex == 1’b1))] |
22 |
`TX_DATA |
`TX_CRS_JAM |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && !(counter[14] == 1’b1 && counter[0] == 1’b1 && po_en_high == 1’b1) && !(pi_valid == 1’b0 && po_en_high == 1’b1) && !(int_eop == 1’b1 && count_60 == 1’b0 && pi_pad == 1’b1 && po_en_high == 1’b1) && !(int_eop == 1’b1 && pi_crc == 1’b1 && po_en_high == 1’b1) && !(int_eop == 1’b1 && count_512 == 1’b0 && burst_begin == 1’b1 && pi_half_duplex == 1’b1) && (int_eop == 1’b1 && po_en_high == 1’b1))] |
23 |
`TX_PAD |
`TX_JAM |
[(!(~ pi_reset) && (gmii_col == 1’b1))] |
24 |
`TX_PAD |
`TX_CRC |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && (count_60 == 1’b1 && po_en_high == 1’b1))] |
25 |
`TX_CRC |
`TX_JAM |
[(!(~ pi_reset) && (gmii_col == 1’b1))] |
26 |
`TX_CRC |
`TX_EXTEND |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && (crc_counter == 2’d3 && count_512 == 1’b0 && burst_begin == 1’b1 && pi_half_duplex == 1’b1))] |
27 |
`TX_CRC |
`TX_CRS_JAM |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && !(crc_counter == 2’d3 && count_512 == 1’b0 && burst_begin == 1’b1 && pi_half_duplex == 1’b1) && ({crc_counter, po_en_high} == {2’d3, 1’b1}))] |
28 |
`TX_EXTEND |
`TX_ERROR |
[(!(~ pi_reset) && (gmii_col == 1’b1))] |
29 |
`TX_EXTEND |
`TX_CRS_ERR |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && (count_512 == 1’b1))] |
30 |
`TX_CRS_JAM |
`TX_JAM |
[(!(~ pi_reset) && (gmii_col == 1’b1))] |
31 |
`TX_CRS_JAM |
`TX_IDLE |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && (gmii_crs == 1’b0 || po_burst_en == 1’b1))] |
32 |
`TX_CRS_ERR |
`TX_ERROR |
[(!(~ pi_reset) && (gmii_col == 1’b1))] |
33 |
`TX_CRS_ERR |
`TX_IDLE |
[(!(~ pi_reset) && !(gmii_col == 1’b1) && (gmii_crs == 1’b0 || po_burst_en == 1’b1))] |
34 |
default |
`TX_IDLE |
[!(~ pi_reset)] |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_tx_topip_mac_tx_top_g
tx_fsm
Global Software/Hardware Reset (transmit clock domain)