Module ip_host_clk_mng_g

ip_host_clk_mng_g u_ip_host_clk_mng_g ( .pi_reset(pi_reset), .pi_sw_reset(pi_sw_reset), .pi_gate_en(pi_gate_en), .po_host_reset(po_host_reset), .po_host_hw_rst(po_host_hw_rst), .pi_power_off(pi_power_off), .pi_host_clock(pi_host_clock), .pi_host_clock_en(pi_host_clock_en), .po_host_clock_f(po_host_clock_f), .po_host_clock_g(po_host_clock_g), .pi_test_en(pi_test_en) );

Block Diagram of ip_host_clk_mng_g

Ports

Name	Direction	Type	Description
pi_reset	input	wire logic	Resets Hardware reset (active low)
pi_sw_reset	input	wire logic	Software reset (active high)
pi_gate_en	input	wire logic	Auto Gating Clock Enable (power saving)
po_host_reset	output	wire logic	Hardware/Software Global output reset (HOST clock domain)
po_host_hw_rst	output	wire logic	Hardware Global output reset (HOST clock domain)
pi_power_off	input	wire logic	Power OFF Power off (all internal clocks are disabled)
pi_host_clock	input	wire logic	Clocks HOST clock used by the reset synchronization block
pi_host_clock_en	input	wire logic[4:0]	HOST clock enable
po_host_clock_f	output	wire logic	Output Host Clock Host Free Clock
po_host_clock_g	output	wire logic[4:0]	Host Gated Clock
pi_test_en	input	wire logic	Test and Scan interface signals Test enable (test clock select)

Instances

• ip_emac_topip_emac_top

  • host_clk_mng

Submodules

• ip_host_clk_mng_g

  • host_free_clock : ip_gate_clock_g

  • host_gate_clock_1 : ip_gate_clock_g

  • host_gate_clock_2 : ip_gate_clock_g

  • host_gate_clock_3 : ip_gate_clock_g

  • host_gate_clock_4 : ip_gate_clock_g

  • host_gate_clock_5 : ip_gate_clock_g

  • host_sreset : ip_sync_reset_g

  • hw_host_sreset : ip_sync_reset_g

Reset

Schematic Diagram of ip_host_clk_mng_g

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