Module ip_mac_hostif_txds

Block Diagram of ip_mac_hostif_txds

Ports
Name	Direction	Type	Description
pi_reset	input	wire logic	Global interface global asynchronous pi_reset
pi_g_clock	input	wire logic	host pi_g_clock
pi_f_clock	input	wire logic	host pi_g_clock
po_en_clock	output	var reg	enable clock condition
po_tx_ds_req	output	var reg	output
po_tx_ds_addr	output	var reg[31:0]	output , mapped to old tx_ds_next_addr
po_tx_ds_addr_valid	output	var reg	output
po_tx_ds_mlast	output	var reg	output
po_tx_ds_mcmd	output	var reg[1:0]	output
po_tx_ds_maddr	output	wire logic[31:0]	output
pi_tx_valid_ds_read	input	wire logic	from pi_mac_hostif_tx (signals that new ds polling is enabled)
pi_host_sdva	input	wire logic
pi_host_sdata	input	wire logic[31:0]
pi_tx_ds_allowed	input	wire logic	`pi_host_serr, //from host interface`
po_tx_ds0_poll	output	var reg[31:0]
pi_tx_ds1	input	wire logic[1:0]	mapped to tx pi_tx_ds1[25:24]
pi_tx_ds3	input	wire logic[31:0]
pi_regs_csr0_tap	input	wire logic[15:0]	Registers bank interface tx automatic polling period CSR0[31:16]
pi_regs_csr0_ape	input	wire logic	tx auto polling enable CSR[15]
pi_regs_csr1_tpd	input	wire logic	transmit poll demand
pi_regs_csr3_stl	input	wire logic[29:0]	transmit descriptor base address
po_regs_csr5_tu	output	var reg	transmit buffer unavailable
pi_regs_csr14_st	input	wire logic	start/stop transmit
pi_config_ds_offset	input	wire logic[4:0]	offset to increment the address if a descriptor

Always Blocks

always @ ( posedge pi_f_clock or negedge pi_reset ) 

FSM Transitions for tx_ds_state
#	Current State	Next State	Condition
1	`TX_DS_IDLE	`TX_DS_MAIN	[(!(~ pi_reset) && !(! pi_regs_csr14_st))]
2	`TX_DS_MAIN	`TX_DS_READ	[(!(~ pi_reset) && (pi_tx_ds_allowed))]
3	`TX_DS_READ	`TX_DS_WAIT	[(!(~ pi_reset) && (pi_host_sdva) && (pi_host_sdata[31]))]
4	`TX_DS_READ	`TX_DS_SUSPEND	[(!(~ pi_reset) && (pi_host_sdva) && !(pi_host_sdata[31]))]
5	`TX_DS_WAIT	`TX_DS_MAIN	[(!(~ pi_reset) && (pi_tx_valid_ds_read))]
6	`TX_DS_SUSPEND	`TX_DS_MAIN	[(!(~ pi_reset) && (pi_regs_csr0_ape && tx_ds_poll_cnt == pi_regs_csr0_tap \|\| pi_regs_csr1_tpd))]

Instances