Module ip_async_fifo_g

MEM_WIDTHpi_reset_wrlogicpi_reset_rdlogicpi_clock_wrlogicpi_clock_rdlogicpi_enable_wrlogicpi_enable_rdlogicpi_data_wr[MEM_WIDTH-1:0]logicpo_full_wrregpo_empty_rdregpo_last_wrregpo_last_rdregpo_data_rdlogic[MEM_WIDTH-1:0]

Block Diagram of ip_async_fifo_g

Overview

Asynchronous FIFOs are used in designs to safely pass multi-bit data words from one clock domain to another.

Data words are placed into a FIFO buffer memory array by:

  • control signals in one clock domain
  • and the data words are removed from another port of the same FIFO buffer memory array by control signals from a second clock domain.
Parameters

Name

Default value

Description

MEM_WIDTH

32

Data width
Ports

Name

Direction

Type

Description

pi_reset_wr

input

wire logic

Write synchronous reset

pi_reset_rd

input

wire logic

Read synchronous reset

pi_clock_wr

input

wire logic

Write clock

pi_clock_rd

input

wire logic

Read clock

pi_enable_wr

input

wire logic

Write enable

pi_enable_rd

input

wire logic

Read enable

po_full_wr

output

var reg

FIFO full indication

po_empty_rd

output

var reg

FIFO empty indication

po_last_wr

output

var reg

FIFO last location for write (almoast full)

po_last_rd

output

var reg

FIFO last location for read (almoast empty)

pi_data_wr

input

wire logic[MEM_WIDTH-1:0]

FIFO data input

po_data_rd

output

wire logic[MEM_WIDTH-1:0]

FIFO data output

Instances

Submodules

cell_0 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_1 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_2 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_3 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_4 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_5 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_6 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd cell_7 (ip_sync_cell) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd po_enable_wr po_enable_rd pi_ready_wr pi_ready_rd ring_wr_1 ring_wr ring_wr_2 ring_wr ring_rd_1 ring_rd ring_rd_2 ring_rd po_data_rd data_rd ring_rd ready_wr pi_enable_wr ring_wr ready_rd pi_enable_rd ring_rd data_rd pi_data_wr ring_wr pi_clock_wr enable_wr pi_enable_wr po_full_wr pi_reset_wr pi_clock_wr enable_wr ring_wr_1 pi_enable_wr ring_wr po_last_wr pi_reset_wr pi_clock_wr enable_wr ring_wr_2 pi_enable_wr ring_wr_1 ring_wr pi_reset_wr pi_clock_wr ring_wr enable_wr pi_enable_wr po_empty_rd pi_reset_rd pi_clock_rd enable_rd ring_rd_1 pi_enable_rd ring_rd po_last_rd pi_reset_rd pi_clock_rd enable_rd ring_rd_2 pi_enable_rd ring_rd_1 ring_rd pi_reset_rd pi_clock_rd ring_rd enable_rd pi_enable_rd rx_async (ip_async_fifo_g) pi_reset_wr pi_reset_rd pi_clock_wr pi_clock_rd pi_enable_wr pi_enable_rd po_full_wr po_empty_rd po_last_wr po_last_rd pi_data_wr po_data_rd

Schematic Diagram of ip_async_fifo_g