Module ip_mac_host_if

ip_mac_host_if u_ip_mac_host_if ( .pi_reset(pi_reset), .pi_sw_reset(pi_sw_reset), .pi_clock(pi_clock), .pi_factor(pi_factor), .pi_base_address(pi_base_address), .po_host_mcmd(po_host_mcmd), .po_host_maddr(po_host_maddr), .po_host_mdata(po_host_mdata), .po_host_mlast(po_host_mlast), .pi_host_sdata(pi_host_sdata), .pi_host_sdva(pi_host_sdva), .pi_host_serr(pi_host_serr), .po_rx_enable_rd(po_rx_enable_rd), .pi_rx_empty(pi_rx_empty), .pi_rx_last_rd(pi_rx_last_rd), .pi_rx_data(pi_rx_data), .pi_rx_sof(pi_rx_sof), .pi_rx_eof(pi_rx_eof), .pi_rx_err(pi_rx_err), .pi_rx_be(pi_rx_be), .po_tx_enable_wr(po_tx_enable_wr), .pi_tx_full(pi_tx_full), .pi_tx_last_wr(pi_tx_last_wr), .po_tx_data(po_tx_data), .po_tx_be(po_tx_be), .po_tx_sof(po_tx_sof), .po_tx_eof(po_tx_eof), .po_tx_put_crc(po_tx_put_crc), .po_tx_put_padding(po_tx_put_padding), .po_tx_upd_read(po_tx_upd_read), .pi_tx_upd_empty(pi_tx_upd_empty), .pi_tx_upd_last(pi_tx_upd_last), .pi_tx_upd_data(pi_tx_upd_data), .pi_regs_csr0_tap(pi_regs_csr0_tap), .pi_regs_csr0_ape(pi_regs_csr0_ape), .pi_regs_csr0_bar(pi_regs_csr0_bar), .pi_regs_csr15_swr(pi_regs_csr15_swr), .pi_regs_csr1_tpd(pi_regs_csr1_tpd), .pi_regs_csr2_rpd(pi_regs_csr2_rpd), .pi_regs_csr3_stl(pi_regs_csr3_stl), .pi_regs_csr4_srl(pi_regs_csr4_srl), .po_regs_csr5_rs(po_regs_csr5_rs), .pi_regs_csr5_rwt(pi_regs_csr5_rwt), .po_regs_csr5_rps(po_regs_csr5_rps), .po_regs_csr5_ru(po_regs_csr5_ru), .po_regs_csr5_tu(po_regs_csr5_tu), .po_regs_csr5_ri(po_regs_csr5_ri), .po_regs_csr5_tjt(po_regs_csr5_tjt), .pi_regs_csr15_st(pi_regs_csr15_st), .pi_regs_csr15_sr(pi_regs_csr15_sr), .po_regs_csr8_mfc_inc(po_regs_csr8_mfc_inc), .pi_config_burst_size(pi_config_burst_size), .pi_config_ds_offset(pi_config_ds_offset), .pi_test_en(pi_test_en), .pi_test_clk(pi_test_clk), .pi_scan_en(pi_scan_en), .pi_scan_in(pi_scan_in), .po_scan_out(po_scan_out) );

Block Diagram of ip_mac_host_if

Ports
Name	Direction	Type	Description
pi_reset	input	wire logic	Global interface global asynchronous reset
pi_sw_reset	input	wire logic	software reset
pi_clock	input	wire logic	host clock
pi_factor	input	wire logic	host clock enable
pi_base_address	input	wire logic[23:0]	HOST Interface device int mem space base address
po_host_mcmd	output	var reg[1:0]	command
po_host_maddr	output	var reg[31:0]	address
po_host_mdata	output	var reg[31:0]	data to write
po_host_mlast	output	var reg	last word
pi_host_sdata	input	wire logic[31:0]	data to read
pi_host_sdva	input	wire logic	data valid
pi_host_serr	input	wire logic	error during last transaction
po_rx_enable_rd	output	wire logic	RX FIFO interface rx fifo read command
pi_rx_empty	input	wire logic	rx fifo full
pi_rx_last_rd	input	wire logic	rx fifo almost full
pi_rx_data	input	wire logic[31:0]	rx fifo data
pi_rx_sof	input	wire logic	rx fifo eof
pi_rx_eof	input	wire logic	rx fifo eof
pi_rx_err	input	wire logic	rx fifo error
pi_rx_be	input	wire logic[1:0]	rx fifo data byte enable
po_tx_enable_wr	output	wire logic	rx fifo read command
pi_tx_full	input	wire logic	rx fifo full
pi_tx_last_wr	input	wire logic	rx fifo almost full
po_tx_data	output	wire logic[31:0]	rx fifo data
po_tx_be	output	wire logic[1:0]	tx fifo data byte enable
po_tx_sof	output	wire logic	tx fifo start of frame
po_tx_eof	output	wire logic	tx fifo end of frame
po_tx_put_crc	output	wire logic	put crc indication (valid only when sof=1)
po_tx_put_padding	output	wire logic	put padding indication (valid only when sof=1)
po_tx_upd_read	output	wire logic	TX update fifo interface
pi_tx_upd_empty	input	wire logic
pi_tx_upd_last	input	wire logic
pi_tx_upd_data	input	wire logic[9:0]
pi_regs_csr0_tap	input	wire logic[15:0]	Registers bank interface tx automatic polling period CSR0[31:16]
pi_regs_csr0_ape	input	wire logic	tx auto polling enable CSR[15]
pi_regs_csr0_bar	input	wire logic	bus arbitration
pi_regs_csr15_swr	input	wire logic	software reset
pi_regs_csr1_tpd	input	wire logic	transmit poll demand
pi_regs_csr2_rpd	input	wire logic	receive poll demand
pi_regs_csr3_stl	input	wire logic[29:0]	transmit descriptor base address
pi_regs_csr4_srl	input	wire logic[29:0]	receive descriptor base address
po_regs_csr5_rs	output	wire logic[1:0]	receive process state
pi_regs_csr5_rwt	input	wire logic	receive watchdog timeout
po_regs_csr5_rps	output	wire logic	receive process stopped
po_regs_csr5_ru	output	var reg	receive buffer unavailable
po_regs_csr5_tu	output	var reg	transmit buffer unavailable
po_regs_csr5_ri	output	wire logic	receive interupt
po_regs_csr5_tjt	output	var reg	signals Transmit jabber timeout error to the CSR5 register; this will signal to the HOST to perform a software reset to the EMAC
pi_regs_csr15_st	input	wire logic	start/stop transmit
pi_regs_csr15_sr	input	wire logic	start / stop receive
po_regs_csr8_mfc_inc	output	wire logic	missed frame counter increment command
pi_config_burst_size	input	wire logic[5:0]	limit for the rx,tx burst transfers
pi_config_ds_offset	input	wire logic[4:0]	pi_rx_mac_ds_poll, //from the RX EMAC part (new frame arrived, or new data arrived) offset to increment the address if a descriptor
pi_test_en	input	wire logic	Test and Scan interface signals Test enable
pi_test_clk	input	wire logic	Test clock
pi_scan_en	input	wire logic	SCAN chain shift enable
pi_scan_in	input	wire logic	SCAN chain input
po_scan_out	output	wire logic	SCAN chain output

Always Blocks